16 Channel, 14-Bit, 65 MSPS, Serial LVDS, 1.8 V ADC Data Sheet AD9249 FEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD Low power AD9249 D+A1 16 ADC channels integrated into 1 package 14 VIN+A1 SERIAL DA1 ADC LVDS VINA1 58 mW per channel at 65 MSPS with scalable power options D+A2 14 VIN+A2 SERIAL 35 mW per channel at 20 MSPS ADC DA2 LVDS VINA2 SNR: 75 dBFS (to Nyquist) SFDR: 90 dBc (to Nyquist) DNL: 0.6 LSB (typical) INL: 0.9 LSB (typical) D+H1 14 VIN+H1 Crosstalk, worst adjacent channel, 10 MHz, 1 dBFS: 90 dB SERIAL DH1 ADC LVDS VINH1 typical D+H2 14 VIN+H2 SERIAL ADC DH2 LVDS Serial LVDS (ANSI-644, default) VINH2 Low power, reduced signal option (similar to IEEE 1596.3) VREF FCO+1, FCO+2 SENSE 1.0V Data and frame clock outputs DATA FCO1, FCO2 VCM1, VCM2 REF RATE 650 MHz full power analog bandwidth DCO+1, DCO+2 SERIAL PORT SELECT MULTIPLIER INTERFACE DCO1, DCO2 SYNC 2 V p-p input voltage range 1.8 V supply operation RBIAS1, GND CSB1, SDIO/ SCLK/ CLK+ CLK RBIAS2 CSB2 DFS DTP Serial port control Figure 1. Flexible bit orientation Built in and custom digital test pattern generation Programmable clock and data alignment Power-down and standby modes APPLICATIONS Medical imaging The ADC contains several features designed to maximize Communications receivers flexibility and minimize system cost, such as programmable Multichannel data acquisition clock and data alignment and programmable digital test pattern generation. GENERAL DESCRIPTION The available digital test patterns include built-in deterministic The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital and pseudorandom patterns, along with custom user-defined test converter (ADC) with an on-chip sample-and-hold circuit that patterns entered via the serial port interface (SPI). is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 65 MSPS and The AD9249 is available in an RoHS-compliant, 144-ball CSP- is optimized for outstanding dynamic performance and low power BGA. It is specified over the industrial temperature range of 40C in applications where a small package size is critical. to +85C. This product is protected by a U.S. patent. The ADC requires a single 1.8 V power supply and an LVPECL-/ PRODUCT HIGHLIGHTS CMOS-/LVDS-compatible sample rate clock for full performance 1. Small Footprint. Sixteen ADCs are contained in a small, operation. No external reference or driver components are 10 mm 10 mm package. required for many applications. 2. Low Power. 35 mW/channel at 20 MSPS with scalable power The AD9249 automatically multiplies the sample rate clock for the options. appropriate LVDS serial data rate. Data clock outputs (DCO1, 3. Ease of Use. Data clock outputs (DCO1, DCO2) operate DCO2) for capturing data on the output and frame clock outputs at frequencies of up to 455 MHz and support double data (FCO1, FCO2) for signaling a new output byte are provided. rate (DDR) operation. Individual channel power-down is supported, and the device 4. User Flexibility. SPI control offers a wide range of flexible typically consumes less than 2 mW when all channels are disabled. features to meet specific system requirements. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 11536-200AD9249 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Outputs and Timing ..................................................... 21 Applications ....................................................................................... 1 Built-In Output Test Modes .......................................................... 25 General Description ......................................................................... 1 Output Test Modes ..................................................................... 25 Simplified Functional Block Diagram ........................................... 1 Serial Port Interface (SPI) .............................................................. 26 Product Highlights ........................................................................... 1 Configuration Using the SPI ..................................................... 26 Revision History ............................................................................... 2 Hardware Interface ..................................................................... 27 Functional Block Diagram .............................................................. 3 Configuration Without the SPI ................................................ 27 Specifications ..................................................................................... 4 SPI Accessible Features .............................................................. 27 DC Specifications ......................................................................... 4 Memory Map .................................................................................. 28 AC Specifications .......................................................................... 5 Reading the Memory Map Register Table ............................... 28 Digital Specifications ................................................................... 6 Memory Map Register Table ..................................................... 29 Switching Specifications .............................................................. 7 Memory Map Register Descriptions ........................................ 32 Timing Specifications .................................................................. 9 Applications Information .............................................................. 34 Absolute Maximum Ratings .......................................................... 10 Design Guidelines ...................................................................... 34 Thermal Characteristics ............................................................ 10 Power and Ground Recommendations ................................... 34 ESD Caution ................................................................................ 10 Board Layout Considerations ................................................... 34 Pin Configuration and Function Descriptions ........................... 11 Clock Stability Considerations ................................................. 35 Typical Performance Characteristics ........................................... 13 VCM ............................................................................................. 35 Equivalent Circuits ......................................................................... 16 Reference Decoupling ................................................................ 35 Theory of Operation ...................................................................... 17 SPI Port ........................................................................................ 35 Analog Input Considerations .................................................... 17 Outline Dimensions ....................................................................... 36 Voltage Reference ....................................................................... 18 Ordering Guide .......................................................................... 36 Clock Input Considerations ...................................................... 19 Power Dissipation and Power-Down Mode ........................... 21 REVISION HISTORY 10/13Revision 0: Initial Version Rev. 0 Page 2 of 36