Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC Data Sheet AD9252 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 8 analog-to-digital converters (ADCs) integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS AD9252 14 SNR = 73 dB (to Nyquist) VIN + A D + A SERIAL ADC D A LVDS VIN A ENOB = 12 bits 14 SFDR = 84 dBc (to Nyquist) VIN + B D + B SERIAL ADC D B Excellent linearity VIN B LVDS 14 DNL = 0.4 LSB (typical) INL = 1.5 LSB (typical) VIN + C D + C SERIAL ADC Serial LVDS (ANSI-644, default) D C VIN C LVDS Low power, reduced signal option (similar to IEEE 1596.3) 14 VIN + D SERIAL D + D Data and frame clock outputs ADC LVDS D D VIN D 325 MHz, full-power analog bandwidth 14 VIN + E SERIAL D + E 2 V p-p input voltage range ADC D E VIN E LVDS 1.8 V supply operation 14 Serial port control VIN + F D + F SERIAL ADC D F VIN F LVDS Full-chip and individual-channel power-down modes 14 Flexible bit orientation VIN + G D + G SERIAL ADC LVDS D G VIN G Built-in and custom digital test pattern generation 14 Programmable clock and data alignment VIN + H D + H SERIAL ADC Programmable output resolution LVDS D H VIN H Standby mode VREF SENSE FCO+ APPLICATIONS 0.5V FCO DATA RATE REFT REF MULTIPLIER Medical imaging and nondestructive ultrasound SERIAL PORT DCO+ REFB SELECT INTERFACE DCO Portable ultrasound and digital beam-forming systems Quadrature radio receivers RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK Diversity radio receivers ODM DTP Tape drives Figure 1. Optical networking The ADC contains several features designed to maximize Test equipment flexibility and minimize system cost, such as programmable GENERAL DESCRIPTION clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip deterministic and pseudorandom patterns, along with custom user- sample-and-hold circuit designed for low cost, low power, small size, defined test patterns entered via the serial port interface (SPI). and ease of use. Operating at a conversion rate of up to 50 MSPS, it is optimized for outstanding dynamic performance and low The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is power in applications where a small package size is critical. specified over the industrial temperature range of 40C to +85C. The ADC requires a single 1.8 V power supply and LVPECL-/ PRODUCT HIGHLIGHTS CMOS-/LVDS-compatible sample rate clock for full performance 1. Small Footprint. Eight ADCs are contained in a small package. operation. No external reference or driver components are 2. Low Power of 93.5 mW per Channel at 50 MSPS. required for many applications. 3. Ease of Use. A data clock output (DCO) operates up to The ADC automatically multiplies the sample rate clock for 350 MHz and supports double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock (DCO) 4. User Flexibility. SPI control offers a wide range of flexible for capturing data on the output and a frame clock (FCO) for features to meet specific system requirements. signaling a new output byte are provided. Individual channel 5. Pin-Compatible Family. This includes the AD9212 (10-bit) power-down is supported and typically consumes less than and AD9222 (12-bit). 2 mW when all channels are disabled. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06296-001AD9252 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 19 Applications ....................................................................................... 1 Serial Port Interface (SPI) .............................................................. 27 General Description ......................................................................... 1 Hardware Interface ..................................................................... 27 Functional Block Diagram .............................................................. 1 Memory Map .................................................................................. 29 Product Highlights ........................................................................... 1 Reading the Memory Map Table .............................................. 29 Revision History ............................................................................... 2 Reserved Locations .................................................................... 29 Specifications ..................................................................................... 3 Default Values ............................................................................. 29 AC Specifications .......................................................................... 4 Logic Levels ................................................................................. 29 Digital Specifications ................................................................... 5 Applications Information .............................................................. 32 Switching Specifications .............................................................. 6 Design Guidelines ...................................................................... 32 Timing Diagrams .......................................................................... 7 Evaluation Board ............................................................................ 33 Absolute Maximum Ratings ............................................................ 9 Power Supplies ............................................................................ 33 Thermal Impedance ..................................................................... 9 Input Signals................................................................................ 33 ESD Caution .................................................................................. 9 Output Signals ............................................................................ 33 Pin Configuration and Function Descriptions ........................... 10 Default Operation and Jumper Selection Settings ................. 34 Equivalent Circuits ......................................................................... 12 Alternative Analog Input Drive Configuration...................... 35 Typical Performance Characteristics ........................................... 14 Outline Dimensions ....................................................................... 52 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 52 Analog Input Considerations .................................................... 17 REVISION HISTORY 12/11Rev. D to Rev. E Changes to Digital Outputs and Timing Section ....................... 24 Changes to Output Signals Section and Figure 58 ..................... 33 Added Table 10 ............................................................................... 24 Change to Default Operation and Jumper Selection Settings Changes to Table 11 and Table 12 ................................................ 24 Section .............................................................................................. 34 Changes to RBIAS Pin Section ..................................................... 25 Added Endnote 2 in Ordering Guide .......................................... 52 Deleted Figure 51 to Figure 52...................................................... 25 Moved Figure 53 ............................................................................. 25 4/10Rev. C to Rev. D Changes to Serial Port Interface (SPI) Section ........................... 27 Changes to Address 16 in Table 16 ............................................... 31 Changes to Table 15 ....................................................................... 28 Updated Outline Dimensions ....................................................... 52 Changes to Reading the Memory Map Table Section ............... 29 Changes to Ordering Guide .......................................................... 52 Added Applications Information and Design Guidelines Sections ...................................................... 32 12/09Rev. B to Rev. C Changes to Input Signals Section ................................................. 33 Updated Outline Dimensions ....................................................... 52 Changes to Output Signals Section .............................................. 33 Changes to Ordering Guide .......................................................... 52 Changes to Figure 60 ...................................................................... 33 Changes to Default Operation and Jumper Selection 7/09Rev. A to Rev. B Settings Section .......................................................................... 34 Changes to Figure 5 ........................................................................ 10 Changes to Alternative Analog Input Drive Changes to Figure 38 and Figure 39 ............................................. 18 Configuration Section............................................................... 35 Changes to Figure 51 and Figure 52 ............................................. 25 Added Figure 62 and Figure 63 .................................................... 35 Updated Outline Dimensions ....................................................... 52 Changes to Figure 68 ...................................................................... 42 12/07Rev. 0 to Rev. A Changes to Table 17 ....................................................................... 48 Changes to Features .......................................................................... 1 Updated Outline Dimensions ....................................................... 52 Changes to Crosstalk Parameter ..................................................... 3 Changes to Ordering Guide .......................................................... 52 Changes to Figure 2 to Figure 4 ...................................................... 7 10/06Revision 0: Initial Version Changes to Table 9 Endnote .......................................................... 23 Rev. E Page 2 of 52