Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC Data Sheet AD9259 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN 4 ADCs integrated into 1 package DRVDD DRGND 98 mW ADC power per channel at 50 MSPS AD9259 14 SNR = 73 dB (to Nyquist) VIN + A SERIAL D + A PIPELINE T/H D A ENOB = 12 bits VIN A LVDS ADC SFDR = 84 dBc (to Nyquist) 14 VIN + B PIPELINE SERIAL D + B Excellent linearity T/H D B VIN B ADC LVDS DNL = 0.5 LSB (typical) 14 VIN + C SERIAL PIPELINE D + C INL = 1.5 LSB (typical) T/H D C VIN C LVDS ADC Serial LVDS (ANSI-644, default) 14 VIN + D Low power, reduced signal option (similar to IEEE 1596.3) SERIAL PIPELINE D + D T/H LVDS D D VIN D ADC Data and frame clock outputs VREF 315 MHz full-power analog bandwidth FCO+ SENSE + 2 V p-p input voltage range 0.5V FCO DATA RATE 1.8 V supply operation REFT REF MULTIPLIER SERIAL PORT DCO+ REFB SELECT Serial port control INTERFACE DCO Full-chip and individual-channel power-down modes RBIASAGND CSB SDIO/ODM SCLK/DTP CLK+ CLK Flexible bit orientation Figure 1. Built-in and custom digital test pattern generation Programmable clock and data alignment The ADC automatically multiplies the sample rate clock for the Programmable output resolution appropriate LVDS serial data rate. A data clock output (DCO) for Standby mode capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel APPLICATIONS power-down is supported and typically consumes less than 2 mW Medical imaging and nondestructive ultrasound when all channels are disabled. Portable ultrasound and digital beam-forming systems Quadrature radio receivers The ADC contains several features designed to maximize flexibility Diversity radio receivers and minimize system cost, such as programmable clock and data Tape drives alignment and programmable digital test pattern generation. The Optical networking available digital test patterns include built-in deterministic and Test equipment pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). GENERAL DESCRIPTION The AD9259 is available in a RoHS-compliant, 48-lead LFCSP. It is The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital con- specified over the industrial temperature range of 40C to +85C. verter (ADC) with an on-chip sample-and-hold circuit designed PRODUCT HIGHLIGHTS for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for 1. Small Footprint. Four ADCs are contained in a small, space- outstanding dynamic performance and low power in applications saving package. where a small package size is critical. 2. Low power of 98 mW/channel at 50 MSPS. 3. Ease of Use. A data clock output (DCO) operates at The ADC requires a single 1.8 V power supply and LVPECL-/ frequencies of up to 350 MHz and supports double data CMOS-/LVDS-compatible sample rate clock for full performance rate (DDR) operation. operation. No external reference or driver components are 4. User Flexibility. The SPI control offers a wide range of flexible required for many applications. features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit). Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Fax: 781.461.3113 20062020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. 05965-001AD9259 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 19 Applications ...................................................................................... 1 Clock Input Considerations ..................................................... 21 General Description ......................................................................... 1 Serial Port Interface (SPI) ............................................................. 29 Functional Block Diagram .............................................................. 1 Hardware Interface .................................................................... 29 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 31 Revision History ............................................................................... 3 Reading the Memory Map Table ............................................. 31 Specifications .................................................................................... 4 Reserved Locations .................................................................... 31 AC Specifications ......................................................................... 5 Default Values ............................................................................ 31 Digital Specifications ................................................................... 6 Logic Levels ................................................................................. 31 Switching Specifications .............................................................. 7 Evaluation Board ............................................................................ 35 Timing Diagrams ......................................................................... 8 Power Supplies ........................................................................... 35 Absolute Maximum Ratings ......................................................... 10 Input Signals ............................................................................... 35 Thermal Impedance ................................................................... 10 Output Signals ............................................................................ 35 ESD Caution................................................................................ 10 Default Operation and Jumper Selection Settings ................ 36 Pin Configuration and Function Descriptions .......................... 11 Alternative Analog Input Drive Configuration ..................... 37 Equivalent Circuits ......................................................................... 13 Outline Dimensions ....................................................................... 51 Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 51 Theory of Operation ...................................................................... 19 Rev. F Page 2 of 52