10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator AD9267 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWNB PDWNA DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input SFDR: 88 dBc to 10 MHz input ORA VIN+A Noise figure: 15 dB D3A - Input impedance: 1 k MODULATOR VINA D0A Power: 416 mW PLL LOCKED 10 MHz real or 20 MHz complex bandwidth PLLMULT4 AD9267 PLLMULT3 1.8 V analog supply operation PLLMULT2 On-chip PLL clock multiplier CLK+ PHASE- On-chip voltage reference VREF LOCKED CLK LOOP Twos complement data format CFILT DCO 640 MSPS, 4-bit LVDS data output VINB D3B Serial control interface (SPI) - MODULATOR VIN+B D0B APPLICATIONS SERIAL ORB Baseband quadrature receivers: CDMA2000, W-CDMA, INTERFACE multicarrier GSM/EDGE, 802.16x, and LTE Quadrature sampling instrumentation AGND SDIO/ SCLK/ CSB DGND PLLMULT1 PLLMULT0 GENERAL DESCRIPTION Figure 1. The AD9267 is a dual continuous time (CT) sigma-delta (-) The AD9267 operates on a 1.8 V power supply, consuming modulator with 88 dBc of dynamic range over 10 MHz real 416 mW. The AD9267 is available in a 64-lead LFCSP and or 20 MHz complex bandwidth. The combination of high is specified over the industrial temperature range (40C dynamic range, wide bandwidth, and characteristics unique to +85C). to the continuous time - modulator architecture makes the PRODUCT HIGHLIGHTS AD9267 an ideal solution for wireless communication systems. 1. Continuous time - architecture efficiently achieves high The AD9267 has a resistive input impedance that significantly dynamic range and wide bandwidth. relaxes the requirements of the driver amplifier. In addition, a 2. Passive input structure reduces or eliminates the require- 32 oversampled fifth-order continuous time loop filter attenuates ments for a driver amplifier. out-of-band signals and aliases, reducing the need for external 3. An oversampling ratio of 32 and high order loop filter filters at the input. The low noise figure of 15 dB relaxes the provide excellent alias rejection, reducing or eliminating linearity requirements of the front-end signal chain components, the need for antialiasing filters. and the high dynamic range reduces the need for an automatic 4. Operates from a single 1.8 V power supply. gain control (AGC) loop. 5. A standard serial port interface (SPI) supports various A differential input clock controls all internal conversion cycles. product features and functions. An external clock input or the integrated integer-N PLL provides 6. Features a low pin count, high speed LVDS interface with the 640 MHz internal clock needed for the oversampled conti- data output clock. nuous time - modulator. The digital output data is presented as 4-bit, LVDS at 640 MSPS in twos complement format. A data clock output (DCO) is provided to ensure proper latch timing with receiving logic. Additional digital signal processing may be required on the 4-bit modulator output to remove the out-of-band noise and to reduce the sample rate. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. LVDS LVDS DRIVERS DRIVERS 07773-001AD9267 TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuits ......................................................................... 12 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13 General Description ......................................................................... 1 Analog Input Considerations ................................................... 13 Functional Block Diagram .............................................................. 1 Clock Input Considerations ...................................................... 14 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 17 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 17 Specif icat ions ..................................................................................... 3 Timing ......................................................................................... 18 DC Specifications ......................................................................... 3 Serial Port Interface (SPI) .............................................................. 19 AC Specifications .......................................................................... 4 Configuration Using the SPI ..................................................... 19 Digital Specifications ................................................................... 5 Hardware Interface ..................................................................... 20 Switching Specifications .............................................................. 6 Applications Information .............................................................. 21 Absolute Maximum Ratings ............................................................ 7 Filtering Requirement ................................................................ 21 Thermal Resistance ...................................................................... 7 Memory Map .................................................................................. 23 ESD Caution .................................................................................. 7 Memory Map Definitions ......................................................... 23 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 24 REVISION HISTORY 7/09Revision 0: Initial Version Rev. 0 Page 2 of 24