8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC) Data Sheet AD9286 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation The AD9286 is an 8-bit, monolithic sampling, analog-to-digital SNR: 49.3 dBFS at 200 MHz input at 500 MSPS converter (ADC) that supports interleaved operation and is SFDR: 65 dBc at 200 MHz input at 500 MSPS optimized for low cost, low power, and ease of use. Each ADC Low power: 315 mW at 500 MSPS operates at up to a 250 MSPS conversion rate with outstanding On-chip interleaved clocking dynamic performance. On-chip reference and track-and-hold The AD9286 takes a single sample clock and, with an on-chip 1.2 V p-p analog input range for each channel clock divider, time interleaves the two ADC cores (each running Differential input with 500 MHz bandwidth at one-half the clock frequency) to achieve the rated 500 MSPS. LVDS-compliant digital output By using the SPI, the user can accurately adjust the timing of the On-chip voltage reference and sample-and-hold circuit sampling edge per ADC to minimize the image spur energy. DNL: 0.2 LSB The ADC requires a single 1.8 V supply and an encode clock Serial port control options for full performance operation. No external reference Interleaved clock timing adjustment components are required for many applications. The digital Offset binary, Gray code, or twos complement data format outputs are LVDS compatible. Optional clock duty cycle stabilizer Built-in selectable digital test pattern generation The AD9286 is available in a Pb-free, 48-lead LFCSP that is Pin-programmable power-down function specified over the industrial temperature range of 40C to +85C. Available in 48-lead LFCSP PRODUCT HIGHLIGHTS APPLICATIONS 1. Integrated 8-Bit, 500 MSPS ADC. Battery-powered instruments 2. Single 1.8 V Supply Operation with LVDS Outputs. Handheld scope meters 3. Power-Down Option Controlled via a Pin-Programmable Low cost digital oscilloscopes Setting. OTS: video over fiber FUNCTIONAL BLOCK DIAGRAM SDIO/ PWDN CSB SCLK OE CLK+ SPI CLK VIN1+ ADC VIN1 VCM D7+ (MSB), D7 (MSB) REF VREF 1.5 SELECT CLOCK D0+ (LSB), D0 (LSB) 1.0V MANAGEMENT V REF VIN2 DCO+ DCO ADC GENERATION VIN2+ DCO AUXCLK AUXCLK+ AD9286 RBIAS AUXCLKEN AGND AVDD DRVDD DRGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20112020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. 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OUTPUT INTERLEAVE LVDS OUTPUT BUFFER 09338-001AD9286 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ...................................................................... 15 Applications ...................................................................................... 1 RBIAS ........................................................................................... 15 General Description ......................................................................... 1 Clock Input Considerations ..................................................... 16 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 18 Functional Block Diagram .............................................................. 1 Built-In Self-Test (BIST) and Output Test ................................. 19 Revision History ............................................................................... 2 Built-In Self-Test (BIST) ........................................................... 19 Specifications .................................................................................... 3 Output Test Modes .................................................................... 19 DC Specifications ......................................................................... 3 Serial Port Interface (SPI) ............................................................. 20 AC Specifications ......................................................................... 4 Configuration Using the SPI .................................................... 20 Digital Specifications ................................................................... 5 Hardware Interface .................................................................... 21 Switching Specifications .............................................................. 6 Configuration Without the SPI ................................................ 21 SPI Timing Specifications ........................................................... 6 SPI Accessible Features ............................................................. 21 Absolute Maximum Ratings ........................................................... 9 Memory Map .................................................................................. 22 Thermal Resistance ...................................................................... 9 Reading the Memory Map Register Table .............................. 22 ESD Caution.................................................................................. 9 Memory Map Register Table .................................................... 23 Pin Configuration and Function Descriptions .......................... 10 Memory Map Register Descriptions ....................................... 25 Typical Performance Characteristics ........................................... 12 Applications Information ............................................................. 26 Equivalent Circuits ......................................................................... 14 Design Guidelines ...................................................................... 26 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 27 ADC Architecture ...................................................................... 15 Ordering Guide .......................................................................... 27 Analog Input Considerations ................................................... 15 REVISION HISTORY 11/2020Rev. C to Rev. D Changed CP-48-12 to CP-48-14 ................................. Throughout 6/2013Rev. A to Rev. B Changes to Figure 6 ........................................................................ 10 Changes to Clock Input Parameters, Table 4 ................................ 6 Updated Outline Dimensions ....................................................... 27 Changes to Clocking Modes Section ........................................... 16 Changes to Ordering Guide .......................................................... 27 Changes to Table 9 ......................................................................... 17 Changes to Register 0x09, Table 13 ............................................. 23 1/2015Rev. B to Rev. C Changes to Table 13 ....................................................................... 24 3/2011Rev. 0 to Rev. A Changes to General Description, ADC Conversion Rate............ 1 1/2011Revision 0: Initial Version Rev. D Page 2 of 27