16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter Data Sheet AD9467 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 SPIVDD DRVDD 75.5 dBFS SNR to 210 MHz at 250 MSPS (1.8V) (3.3V) (1.8V) (1.8V TO 3.3V) (1.8V) 90 dBFS SFDR to 300 MHz at 250 MSPS CSB AD9467 SFDR at 170 MHz at 250 MSPS SDIO BUFFER SCLK 92 dBFS at 1 dBFS VIN+ 16 100 dBFS at 2 dBFS PIPELINE 2 OR+/OR ADC LVDS VIN 60 fs rms jitter OUTPUT D15+/D15 16 STAGING Excellent linearity at 250 MSPS TO D0+/D0 DNL = 0.5 LSB typical CLK+ CLOCK 2 AND TIMING DCO+/DCO INL = 3.5 LSB typical REF CLK MANAGEMENT 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable) AGND XVREF DRGND Integrated input buffer Figure 1. External reference support option Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation A data clock output (DCO) for capturing data on the output is APPLICATIONS provided for signaling a new output bit. Multicarrier, multimode cellular receivers The internal power-down feature supported via the SPI typically Antenna array positioning consumes less than 5 mW when disabled. Power amplifier linearization Optional features allow users to implement various selectable Broadband wireless operating conditions, including input range, data format select, Radar and output data test patterns. Infrared imaging Communications instrumentation The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the 40C to +85C industrial temperature range. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9467 is a 16-bit, monolithic, IF sampling analog-to- 1. IF optimization capability used to improve SFDR. digital converter (ADC). It is optimized for high performance 2. Outstanding SFDR performance for IF sampling over wide bandwidths and ease of use. The product operates at a applications such as multicarrier, multimode 3G, and 4G 250 MSPS conversion rate and is designed for wireless receivers, cellular base station receivers. instrumentation, and test equipment that require a high 3. Ease of use: on-chip reference, high input impedance dynamic range. buffer, adjustable analog input range, and an output clock to simplify data capture. The ADC requires 1.8 V and 3.3 V power supplies and a low 4. Packaged in a Pb-free, 72-lead LFCSP package. voltage differential input clock for full performance operation. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC No external reference or driver components are required for performance over a wide range of input clock pulse widths. many applications. Data outputs are LVDS compatible (ANSI-644 6. Standard serial port interface (SPI) supports various compatible) and include the means to reduce the overall current product features and functions, such as data formatting needed for short trace distances. (offset binary, twos complement, or Gray coding). Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102013 Analog Devices, Inc. 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Technical Support www.analog.com 09029-001AD9467 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuits ......................................................................... 11 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 19 Functional Block Diagram .............................................................. 1 Analog Input Considerations ................................................... 19 Product Highlights ........................................................................... 1 Clock Input Considerations ...................................................... 22 Revision History ............................................................................... 2 Serial Port Interface (SPI) .............................................................. 26 Specifications ..................................................................................... 3 Hardware Interface ..................................................................... 26 AC Specifications .......................................................................... 4 Memory Map .................................................................................. 28 Digital Specifications ................................................................... 6 Reading the Memory Map Table .............................................. 28 Switching Specifications .............................................................. 7 Reserved Locations .................................................................... 28 Absolute Maximum Ratings ............................................................ 8 Default Values ............................................................................. 28 Thermal Impedance ..................................................................... 8 Logic Levels ................................................................................. 28 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 32 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 32 REVISION HISTORY 2/13Rev. C to Rev. D 2/11Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Features Section ............................................................ 1 Changes to Figure 2 .......................................................................... 7 Added Figure 24 and Figure 25 Renumbered Sequentially ..... 14 Changes to VIN+, VIN Parameter Rating, Table 5 ................... 8 Changes to Differential Configurations Section and Changes to Figure 51, Figure 52, and Figure 53 ......................... 20 Figure 54 .......................................................................................... 21 Changes to Figure 54 and Figure 56 ............................................. 21 Added Figure 55 to Figure 57 ....................................................... 21 Changes to Digital Outputs and Timing Section ....................... 24 Changes to Figure 65 and Figure 66 ............................................ 24 Deleted Addr. (Hex) 17 Row, Table 13 ......................................... 29 Changes to Addr. (Hex) 15, Bits 2:0 , Addr. (Hex) 10, Bits 7:0 , Updated Outline Dimensions ....................................................... 32 and Addr. (Hex) 10, Default Notes Column ............................... 29 Changes to Ordering Guide .......................................................... 32 Changes to Addr. (Hex) 36, Default Value (Hex) Column and Addr. (Hex) 107, Default Value (Hex) Column ......................... 30 9/11Rev. B to Rev. C Changes to Figure 44 and Figure 45 ............................................. 17 10/10Revision 0: Initial Version 3/11Rev. A to Rev. B Change Parameter Name to Full Power Bandwidth, Table 1 ...... 3 Changes to Switching Specifications, Table 4 ............................... 7 Change to VIN+, VIN Parameter, Table 5 .................................. 8 Deleted Figure 43 ............................................................................ 17 Added New Figure 43..................................................................... 17 Rev. D Page 2 of 32