8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter AD9484 FEATURES FUNCTIONAL BLOCK DIAGRAM VREF PWDN AGND AVDD SNR = 47 dBFS at f up to 250 MHz at 500 MSPS IN ENOB of 7.5 bits at f up to 250 MHz at 500 MSPS (1.0 dBFS) IN REFERENCE AD9484 SFDR = 79 dBc at f up to 250 MHz at 500 MSPS (1.0 dBFS) IN CML Integrated input buffer DRVDD DRGND Excellent linearity VIN+ TRACK-AND-HOLD VIN DNL = 0.1 LSB typical ADC 8 OUTPUT 8 CORE STAGING D7 TO D0 INL = 0.1 LSB typical LVDS LVDS at 500 MSPS (ANSI-644 levels) CLK+ CLOCK OR+ MANAGEMENT CLK 1 GHz full power analog bandwidth OR On-chip reference, no external decoupling required SERIAL PORT Low power dissipation DCO+ DCO 670 mW at 500 MSPSLVDS SDR output Programmable (nominal) input voltage range SCLK/DFS SDIO CSB 1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal Figure 1. 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Low cost digital oscilloscopes Satellite subsystems Power amplifier linearization GENERAL DESCRIPTION The AD9484 is an 8-bit, monolithic, sampling analog-to-digital Fabricated on an advanced BiCMOS process, the AD9484 is availa- converter (ADC) optimized for high performance, low power, ble in a 56-lead LFCSP, and is specified over the industrial and ease of use. The part operates at up to a 500 MSPS conver- temperature range (40C to +85C). This product is protected sion rate and is optimized for outstanding dynamic performance by a U.S. patent. in wideband carrier and broadband systems. All necessary PRODUCT HIGHLIGHTS functions, including a sample-and-hold and voltage reference, 1. High Performance. are included on the chip to provide a complete signal conversion Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input. solution. The VREF pin can be used to monitor the internal 2. Ease of Use. reference or provide an external voltage reference (external LVDS output data and output clock signal allow interface reference mode must be enabled through the SPI port). to current FPGA technology. The on-chip reference and The ADC requires a 1.8 V analog voltage supply and a differen- sample-and-hold provide flexibility in system design. Use tial clock for full performance operation. The digital outputs are of a single 1.8 V supply simplifies system power supply design. LVDS (ANSI-644) compatible and support twos complement, 3. Serial Port Control. offset binary format, or Gray code. A data clock output is available Standard serial port interface supports various product for proper output data timing. functions, such as data formatting, power-down, gain adjust, and output test pattern generation. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09615-001AD9484 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Analog Input and Voltage Reference ....................................... 14 Functional Block Diagram .............................................................. 1 Clock Input Considerations ...................................................... 15 General Description ......................................................................... 1 Power Dissipation and Power-Down Mode ........................... 16 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 16 Revision History ............................................................................... 2 Timing ......................................................................................... 17 Specif icat ions ..................................................................................... 3 VREF ............................................................................................ 17 DC Specifications ......................................................................... 3 AD9484 Configuration Using the SPI ..................................... 18 AC Specifications .......................................................................... 4 Hardware Interface ..................................................................... 18 Digital Specifications ................................................................... 5 Configuration Without the SPI ................................................ 18 Switching Specifications .............................................................. 6 Memory Map .................................................................................. 20 Absolute Maximum Ratings ............................................................ 7 Reading the Memory Map Table .............................................. 20 Thermal Resistance ...................................................................... 7 Reserved Locations .................................................................... 20 ESD Caution .................................................................................. 7 Default Values ............................................................................. 20 Pin Configuration and Function Descriptions ............................. 8 Logic Levels ................................................................................. 20 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 23 Equivalent Circuits ......................................................................... 13 Ordering Guide .......................................................................... 23 REVISION HISTORY 6/11Rev. 0 to Rev. A Change to General Description Section ........................................ 1 Change to Aperture Time Parameter in Table 4 ........................... 6 Change to Figure 34 ....................................................................... 16 Changes to Register 17 and Register 18 in Table 12 .................. 20 3/11Revision 0: Initial Version Rev. A Page 2 of 24