1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs Data Sheet AD9510 FEATURES FUNCTIONAL BLOCK DIAGRAM VS GND RSET CPRSET VCP Low phase noise phase-locked loop core Reference input frequencies to 250 MHz DISTRIBUTION PLL AD9510 REF REF Programmable dual modulus prescaler REFIN R DIVIDER PHASE CHARGE REFINB Programmable charge pump (CP) current FREQUENCY CP PUMP DETECTOR N DIVIDER Separate CP supply (VCP ) extends tuning range S SYNCB, FUNCTION RESETB PLL PDB Two 1.6 GHz, differential clock inputs STATUS SETTINGS 8 programmable dividers, 1 to 32, all integers CLK1 CLK2 CLK1B CLK2B Phase select for output-to-output coarse delay adjust PROGRAMMABLE DIVIDERS AND 4 independent 1.2 GHz LVPECL outputs PHASE ADJUST LVPECL OUT0 /1, /2, /3... /31, /32 Additive output jitter of 225 fs rms OUT0B LVPECL 4 independent 800 MHz low voltage differential signaling OUT1 /1, /2, /3... /31, /32 (LVDS) or 250 MHz complementary metal oxide conductor OUT1B LVPECL (CMOS) clock outputs OUT2 /1, /2, /3... /31, /32 Additive output jitter of 275 fs rms OUT2B SCLK LVPECL Fine delay adjust on 2 LVDS/CMOS outputs SERIAL OUT3 SDIO CONTROL /1, /2, /3... /31, /32 SDO Serial control port PORT OUT3B CSB LVDS/CMOS Space-saving 64-lead LFCSP OUT4 /1, /2, /3... /31, /32 OUT4B APPLICATIONS LVDS/CMOS OUT5 /1, /2, /3... /31, /32 T Low jitter, low phase noise clock distribution OUT5B LVDS/CMOS Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and OUT6 /1, /2, /3... /31, /32 T OUT6B mixed-signal front ends (MxFEs) LVDS/CMOS High performance wireless transceivers OUT7 /1, /2, /3... /31, /32 OUT7B High performance instrumentation Broadband infrastructure Figure 1. GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function Each output has a programmable divider that can be bypassed along with an on-chip phase-locked loop (PLL) core. The design or set to divide by any integer up to 32. The phase of one clock emphasizes low jitter and phase noise to maximize data converter output relative to another clock output can be varied by means performance. Other applications with demanding phase noise of a divider phase select function that serves as a coarse timing and jitter requirements also benefit from this device. adjustment. Two of the LVDS/CMOS outputs feature program- mable delay elements with full-scale ranges up to 8 ns of delay. The PLL section consists of a programmable reference divider This fine tuning delay block has 5-bit resolution, giving 25 (R) a low noise, phase frequency detector (PFD) a precision possible delays from which to choose for each full-scale setting charge pump (CP) and a programmable feedback divider (N). (Register 0x36 and Register 0x3A = 00000b to 11000b). By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 The AD9510 is ideally suited for data converter clocking and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized applications where maximum converter performance is to the input reference. achieved by encode signals with subpicosecond jitter. There are eight independent clock outputs. Four outputs are low The AD9510 is available in a 64-lead LFCSP and can be operated voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz, from a single 3.3 V supply. An external VCO, which requires an and four are selectable as either LVDS (800 MHz) or CMOS extended voltage range, can be accommodated by connecting (250 MHz) levels. the charge pump supply (VCP) to 5.5 V. The temperature range is 40C to +85C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 05046-001AD9510 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overall ......................................................................................... 28 Applications ....................................................................................... 1 PLL Section ................................................................................. 28 Functional Block Diagram .............................................................. 1 FUNCTION Pin ......................................................................... 32 General Description ......................................................................... 1 Distribution Section ................................................................... 32 Revision History ............................................................................... 2 CLK1 and CLK2 Clock Inputs .................................................. 32 Specifications ..................................................................................... 4 Dividers........................................................................................ 32 PLL Characteristics ...................................................................... 4 Delay Block ................................................................................. 37 Clock Inputs .................................................................................. 5 Outputs ........................................................................................ 37 Clock Outputs ............................................................................... 6 Power-Down Modes .................................................................. 38 Timing Characteristics ................................................................ 6 Reset Modes ................................................................................ 38 Clock Output Phase Noise .......................................................... 8 Single-Chip Synchronization .................................................... 39 Clock Output Additive Time Jitter ........................................... 11 Multichip Synchronization ....................................................... 39 PLL and Distribution Phase Noise and Spurious ................... 13 Serial Control Port ......................................................................... 40 Serial Control Port ..................................................................... 13 Serial Control Port Pin Descriptions ....................................... 40 FUNCTION Pin ......................................................................... 14 General Operation of Serial Control Port ............................... 40 STATUS Pin ................................................................................ 14 The Instruction Word (16 Bits) ................................................ 41 Power ............................................................................................ 15 MSB/LSB First Transfers ........................................................... 41 Timing Diagrams ............................................................................ 16 Register Map and Description ...................................................... 44 Absolute Maximum Ratings .......................................................... 17 Summary Table ........................................................................... 44 Thermal Characteristics ............................................................ 17 Register Map Description ......................................................... 46 ESD Caution ................................................................................ 17 Power Supply ................................................................................... 53 Pin Configuration and Function Descriptions ........................... 18 Power Management.................................................................... 53 Typical Performance Characteristics ........................................... 20 Applications Information .............................................................. 54 Terminology .................................................................................... 24 Using the AD9510 Outputs for ADC Clock Applications .... 54 Typical Modes of Operation .......................................................... 25 CMOS Clock Distribution ........................................................ 54 PLL with External VCXO/VCO Followed by Clock LVPECL Clock Distribution ..................................................... 55 Distribution ................................................................................. 25 LVDS Clock Distribution .......................................................... 55 Clock Distribution Only ............................................................ 25 Power and Grounding Considerations and Power Supply PLL with External VCO and Band-Pass Filter Followed by Rejection ...................................................................................... 55 Clock Distribution ...................................................................... 26 Outline Dimensions ....................................................................... 56 Functional Description .................................................................. 28 Ordering Guide .......................................................................... 56 REVISION HISTORY 9/2016Rev. B to Rev. C Added EPAD Row, Table 14 .......................................................... 19 Changes to STATUS Pin Section .................................................. 30 Changes to Figure 21...................................................................... 22 Changes to Ordering Guide .......................................................... 56 Changes to Delay Block Section, Figure 40, and Calculating the Delay Section................................................................................... 37 9/2013Rev. A to Rev. B Changes to Address 0x36 5:1 and Address 0x3A 5:1 , Changes to General Description Section ...................................... 1 Table 24 ............................................................................................ 44 Changes to Table 4 ............................................................................ 6 Changes to Address 0x36 and Address 0x3A, Table 25 ............. 49 Changes to Table 6 .......................................................................... 11 Updated Outline Dimensions ....................................................... 56 Added Table 13 Renumbered Sequentially ................................ 17 Changes to Ordering Guide .......................................................... 56 Changes to Figure 6 ........................................................................ 18 Rev. C Page 2 of 56