14-Output Clock Generator with Integrated 2.0 GHz VCO Data Sheet AD9516-3 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.75 GHz to 2.25 GHz External VCO/VCXO to 2.4 GHz optional REF1 STATUS MONITOR 1 differential or 2 single-ended reference inputs REFIN Reference monitoring capability VCO REF2 Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz DIVIDER CLK AND MUXs Programmable delays in path to PFD Digital or analog lock detect, selectable OUT0 DIV/ LVPECL 6 pairs of 1.6 GHz LVPECL outputs OUT1 OUT2 Each output pair shares a 1-to-32 divider with coarse DIV/ LVPECL OUT3 phase delay OUT4 DIV/ LVPECL OUT5 Additive output jitter: 225 fs rms t OUT6 DIV/ DIV/ LVDS/CMOS Channel-to-channel skew paired outputs of <10 ps t OUT7 t OUT8 4 pairs of 800 MHz LVDS clock outputs DIV/ DIV/ LVDS/CMOS t OUT9 Each output pair shares two cascaded 1-to-32 dividers SERIAL CONTROL PORT with coarse phase delay AND AD9516-3 DIGITAL LOGIC Additive output jitter: 275 fs rms Fine delay adjust (t) on each LVDS output Figure 1. Each LVDS output can be reconfigured as two 250 MHz CMOS outputs Automatic synchronization of all outputs on power-up Manual output synchronization available The AD9516-3 features six LVPECL outputs (in three pairs) 64-lead LFCSP and four LVDS outputs (in two pairs). Each LVDS output can APPLICATIONS be reconfigured as two CMOS outputs. The LVPECL outputs Low jitter, low phase noise clock distribution operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and 10/40/100 Gb/sec networking line cards, including SONET, the CMOS outputs operate to 250 MHz. Synchronous Ethernet, OTU2/3/4 Each pair of outputs has dividers that allow both the divide Forward error correction (G.710) ratio and coarse delay (or phase) to be set. The range of division Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs High performance wireless transceivers allow a range of divisions up to a maximum of 1024. ATE and high performance instrumentation The AD9516-3 is available in a 64-lead LFCSP and can be GENERAL DESCRIPTION operated from a single 3.3 V supply. An external VCO, which 1 The AD9516-3 provides a multi-output clock distribution requires an extended voltage range, can be accommodated function with subpicosecond jitter performance, along with an on- by connecting the charge pump supply (VCP) to 5 V. A separate chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to LVPECL power supply can be from 2.5 V to 3.3 V (nominal). 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz The AD9516-3 is specified for operation over the standard can be used. industrial range of 40C to +85C. The AD9516-3 emphasizes low jitter and phase noise to 1 AD9516 is used throughout to refer to all the members of the AD9516 family. maximize data converter performance, and it can benefit other However, when AD9516-3 is used, it refers to that specific member of the applications with demanding phase noise and jitter requirements. AD9516 family. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com SWITCHOVER AND MONITOR PLL 06422-001AD9516-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 16 Applications ....................................................................................... 1 ESD Caution................................................................................ 16 General Description ......................................................................... 1 Pin Configuration and Function Descriptions ........................... 17 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 19 Revision History ............................................................................... 3 Terminology .................................................................................... 25 Specifications ..................................................................................... 4 Detailed Block Diagram ................................................................ 26 Power Supply Requirements ....................................................... 4 Theory of Operation ...................................................................... 27 PLL Characteristics ...................................................................... 4 Operational Configurations ...................................................... 27 Clock Inputs .................................................................................. 6 Digital Lock Detect (DLD) ....................................................... 36 Clock Outputs ............................................................................... 6 Clock Distribution ..................................................................... 40 Timing Characteristics ................................................................ 7 Reset Modes ................................................................................ 48 Clock Output Additive Phase Noise (Distribution Only VCO Power-Down Modes .................................................................. 49 Divider Not Used) ........................................................................ 8 Serial Control Port ......................................................................... 50 Clock Output Absolute Phase Noise (Internal VCO Used) .... 9 Serial Control Port Pin Descriptions ....................................... 50 Clock Output Absolute Time Jitter (Clock Generation Using General Operation of Serial Control Port ............................... 50 Internal VCO) ............................................................................. 10 The Instruction Word (16 Bits) ................................................ 51 Clock Output Absolute Time Jitter (Clock Cleanup Using MSB/LSB First Transfers ........................................................... 51 Internal VCO) ............................................................................. 10 Thermal Performance .................................................................... 54 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 10 Register Map Overview ................................................................. 55 Clock Output Additive Time Jitter (VCO Divider Not Used) Register Map Descriptions ............................................................ 59 ....................................................................................................... 11 Applications Information .............................................................. 77 Clock Output Additive Time Jitter (VCO Divider Used) ..... 11 Frequency Planning Using the AD9516 .................................. 77 Delay Block Additive Time Jitter .............................................. 12 Using the AD9516 Outputs for ADC Clock Applications .... 77 Serial Control Port ..................................................................... 12 LVPECL Clock Distribution ..................................................... 78 PD, RESET, and SYNC Pins ..................................................... 13 LVDS Clock Distribution .......................................................... 78 LD, STATUS, and REFMON Pins ............................................ 13 CMOS Clock Distribution ........................................................ 79 Power Dissipation ....................................................................... 14 Outline Dimensions ....................................................................... 80 Timing Diagrams ............................................................................ 15 Ordering Guide .......................................................................... 80 Absolute Maximum Ratings .......................................................... 16 Rev. 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