12-Output Clock Generator with Integrated 2.5 GHz VCO Data Sheet AD9517-1 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.30 GHz to 2.65 GHz External VCO/VCXO to 2.4 GHz optional REF1 STATUS MONITOR 1 differential or 2 single-ended reference inputs REFIN Reference monitoring capability VCO REF2 Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz DIVIDER CLK AND MUXs Programmable delays in path to PFD Digital or analog lock detect, selectable OUT0 DIV/ LVPECL 2 pairs of 1.6 GHz LVPECL outputs OUT1 OUT2 Each output pair shares a 1-to-32 divider with coarse DIV/ LVPECL OUT3 phase delay t OUT4 DIV/ DIV/ LVDS/CMOS t OUT5 Additive output jitter: 225 fs rms t OUT6 DIV/ DIV/ LVDS/CMOS Channel-to-channel skew paired outputs of <10 ps t OUT7 2 pairs of 800 MHz LVDS clock outputs SERIAL CONTROL PORT AND AD9517-1 Each output pair shares two cascaded 1-to-32 dividers DIGITAL LOGIC with coarse phase delay Additive output jitter: 275 fs rms Figure 1. Fine delay adjust (t) on each LVDS output The AD9517-1 features four LVPECL outputs (in two pairs) Each LVDS output can be reconfigured as two 250 MHz and four LVDS outputs (in two pairs). Each LVDS output can CMOS outputs be reconfigured as two CMOS outputs. The LVPECL outputs Automatic synchronization of all outputs on power-up operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and Manual output synchronization available the CMOS outputs operate to 250 MHz. Available in a 48-lead LFCSP For applications that require additional outputs, a crystal reference APPLICATIONS input, zero-delay, or EEPROM for automatic configuration at Low jitter, low phase noise clock distribution startup, the AD9520 and AD9522 are available. In addition, 10/40/100 Gb/sec networking line cards, including SONET, the AD9516 and AD9518 are similar to the AD9517 but have Synchronous Ethernet, OTU2/3/4 a different combination of outputs. Forward error correction (G.710) Each pair of outputs has dividers that allow both the divide Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs ratio and coarse delay (or phase) to be set. The range of division High performance wireless transceivers for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs ATE and high performance instrumentation allow a range of divisions up to a maximum of 1024. GENERAL DESCRIPTION The AD9517-1 is available in a 48-lead LFCSP and can be 1 The AD9517-1 provides a multi-output clock distribution operated from a single 3.3 V supply. An external VCO, which function with subpicosecond jitter performance, along with an requires an extended voltage range, can be accommodated on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz by connecting the charge pump supply (VCP) to 5 V. A to 2.65 GHz. Optionally, an external VCO/VCXO of up to separate LVPECL power supply can be from 2.5 V to 3.3 V 2.4 GHz can be used. (nominal). The AD9517-1 emphasizes low jitter and phase noise to The AD9517-1 is specified for operation over the industrial maximize data converter performance, and it can benefit other range of 40C to +85C. applications with demanding phase noise and jitter requirements. 1 AD9517 is used throughout the data sheet to refer to all the members of the AD9517 family. However, when AD9517-1 is used, it refers to that specific member of the AD9517 family. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20072020 Analog Devices, Inc. All rights reserved. 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SWITCHOVER AND MONITOR PLL 06425-001AD9517-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution ............................................................................... 17 Applications ...................................................................................... 1 Pin Configuration and Function Descriptions .......................... 18 General Description ......................................................................... 1 Typical Performance Characteristics .......................................... 20 Functional Block Diagram .............................................................. 1 Terminology .................................................................................... 26 Revision History ............................................................................... 3 Detailed Block Diagram ................................................................ 27 Specifications .................................................................................... 4 Theory of Operation ...................................................................... 28 Power Supply Requirements ....................................................... 4 Operational Configurations...................................................... 28 PLL Characteristics ...................................................................... 4 Digital Lock Detect (DLD) ....................................................... 37 Clock Inputs .................................................................................. 6 Clock Distribution ..................................................................... 41 Clock Outputs ............................................................................... 6 Reset Modes ................................................................................ 49 Timing Characteristics ................................................................ 8 Power-Down Modes .................................................................. 50 Clock Output Additive Phase Noise (Distribution Only Serial Control Port ......................................................................... 51 VCO Divider Not Used).............................................................. 9 Serial Control Port Pin Descriptions ....................................... 51 Clock Output Absolute Phase Noise (Internal VCO Used) . 10 General Operation of Serial Control Port .............................. 51 Clock Output Absolute Time Jitter (Clock Generation Using The Instruction Word (16 Bits) ............................................... 52 Internal VCO) ............................................................................. 11 MSB/LSB First Transfers ........................................................... 52 Clock Output Absolute Time Jitter (Clock Cleanup Using Thermal Performance .................................................................... 55 Internal VCO) ............................................................................. 11 Control Registers ............................................................................ 56 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 11 Control Register Map Overview .............................................. 56 Clock Output Additive Time Jitter (VCO Divider Not Used) Control Register Map Descriptions ......................................... 59 ....................................................................................................... 12 Applications Information ............................................................. 76 Clock Output Additive Time Jitter (VCO Divider Used) .... 12 Frequency Planning Using the AD9517 ................................. 76 Delay Block Additive Time Jitter ............................................. 13 Using the AD9517 Outputs for ADC Clock Applications ... 76 Serial Control Port ..................................................................... 13 LVPECL Clock Distribution ..................................................... 77 PD, SYNC, and RESET Pins ..................................................... 14 LVDS Clock Distribution.......................................................... 77 LD, STATUS, and REFMON Pins ........................................... 14 CMOS Clock Distribution ........................................................ 78 Power Dissipation ...................................................................... 15 Outline Dimensions ....................................................................... 79 Timing Diagrams ............................................................................ 16 Ordering Guide .......................................................................... 79 Absolute Maximum Ratings ......................................................... 17 Thermal Resistance .................................................................... 17 Rev. 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