12 LVDS/24 CMOS Output Clock Generator Data Sheet AD9522-5 FEATURES FUNCTIONAL BLOCK DIAGRAM CP Low phase noise, phase-locked loop (PLL) Supports external 3.3 V/5 V voltage controlled oscillator (VCO)/VCXO to 2.4 GHz STATUS REF1 MONITOR 1 differential or 2 single-ended reference inputs REFIN Accepts CMOS, LVPECL, or LVDS references to 250 MHz REFIN REF2 Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler ZERO DELAY Reference monitoring capability DIVIDER CLK AND MUXES Revertive automatic and manual reference switchover/ LVDS/ holdover modes CMOS OUT0 Glitch-free switchover between references DIV/ OUT1 OUT2 Automatic recovery from holdover OUT3 Digital or analog lock detect, selectable DIV/ OUT4 OUT5 Optional zero delay operation OUT6 Twelve 800 MHz LVDS outputs divided into 4 groups OUT7 DIV/ OUT8 Each group of 3 has a 1-to-32 divider with phase delay OUT9 Additive output jitter as low as 242 fs rms OUT10 DIV/ Channel-to-channel skew grouped outputs < 60 ps OUT11 Each LVDS output can be configured as 2 CMOS outputs 2 SPI/I C CONTROL (for f 250 MHz) OUT PORT AND EEPROM AD9522-5 DIGITAL LOGIC Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed Figure 1. SPI- and IC-compatible serial control port The AD9522 serial interface supports both SPI and I2C ports. 64-lead LFCSP An in-package EEPROM can be programmed through the Nonvolatile EEPROM stores configuration settings serial interface and store user-defined register settings for APPLICATIONS power-up and chip reset. Low jitter, low phase noise clock distribution The AD9522 features 12 LVDS outputs in four groups. Any of Clock generation and translation for SONET, 10Ge, 10G FC, the 800 MHz LVDS outputs can be reconfigured as two and other 10 Gbps protocols 250 MHz CMOS outputs. Forward error correction (G.710) Each group of outputs has a divider that allows both the divide Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs ratio (from 1 to 32) and the phase (coarse delay) to be set. High performance wireless transceivers ATE and high performance instrumentation The AD9522 is available in a 64-lead LFCSP and can be operated Broadband infrastructures from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. The AD9522 is specified for operation over the standard industrial GENERAL DESCRIPTION range of 40C to +85C. 1 The AD9522-5 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL The AD9520-5 is an equivalent part to the AD9522-5 featuring that can be used with an external VCO. LVPECL/CMOS drivers instead of LVDS/CMOS drivers. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific member of the AD9522 family. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SWITCHOVER AND MONITOR PLL 07240-001AD9522-5 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Charge Pump (CP) ................................................................. 30 Applications ....................................................................................... 1 PLL External Loop Filter ....................................................... 31 General Description ......................................................................... 1 PLL Reference Inputs ............................................................. 31 Functional Block Diagram .............................................................. 1 Reference Switchover ............................................................. 31 Revision History ............................................................................... 4 Reference Divider R ............................................................... 32 Specifications ..................................................................................... 5 VCO/VCXO Feedback Divider N: P, A, B .......................... 32 Power Supply Requirements ....................................................... 5 Digital Lock Detect (DLD) ................................................... 33 PLL Characteristics ...................................................................... 5 Analog Lock Detect (ALD) ................................................... 33 Clock Inputs .................................................................................. 8 Current Source Digital Lock Detect (CSDLD) .................. 33 Clock Outputs ............................................................................... 8 External VCXO/VCO Clock Input (CLK/CLK) ................ 34 Timing Characteristics ................................................................ 9 Holdover .................................................................................. 34 Timing Diagrams ..................................................................... 9 External/Manual Holdover Mode ........................................ 34 Clock Output Additive Phase Noise (Distribution Only VCO Automatic/Internal Holdover Mode .................................... 35 Divider Not Used) ...................................................................... 10 Frequency Status Monitors ................................................... 36 Clock Output Absolute Time Jitter (Clock Generation Using Zero Delay Operation ................................................................ 37 External VCXO) ......................................................................... 11 Clock Distribution ..................................................................... 38 Clock Output Additive Time Jitter (VCO Divider Not Used) Operation Modes ................................................................... 38 ....................................................................................................... 11 Clock Frequency Division ..................................................... 38 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 VCO Divider ........................................................................... 39 Serial Control PortSPI Mode ................................................ 12 Channel Dividers ................................................................... 39 Serial Control PortIC Mode ................................................ 13 SYNC Synchronizing the Outputs Function ................... 41 PD SYNC RESET , , and Pins ..................................................... 14 LVDS Output Drivers ............................................................ 42 Serial Port Setup Pins: SP1, SP0 ............................................... 14 CMOS Output Drivers .......................................................... 43 LD, STATUS, and REFMON Pins ............................................ 14 Reset Modes ................................................................................ 43 Power Dissipation ....................................................................... 15 Power-On Reset ...................................................................... 43 Absolute Maximum Ratings .......................................................... 16 Hardware Reset via the RESET Pin ..................................... 43 Thermal Resistance .................................................................... 16 Soft Reset via the Serial Port ................................................. 43 ESD Caution ................................................................................ 16 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via Pin Configuration and Function Descriptions ........................... 17 the Serial Port ......................................................................... 43 Typical Performance Characteristics ........................................... 20 Power-Down Modes .................................................................. 43 Terminology .................................................................................... 24 Chip Power-Down via PD..................................................... 43 Detailed Block Diagram ................................................................ 25 PLL Power-Down ................................................................... 44 Theory of Operation ...................................................................... 26 Distribution Power-Down .................................................... 44 Operational Configurations ...................................................... 26 Individual Clock Output Power-Down ............................... 44 Mode 1: Clock Distribution or External VCO < 1600 MHz Individual Clock Channel Power-Down ............................. 44 ................................................................................................... 26 Serial Control Port ......................................................................... 45 Mode 2: High Frequency Clock DistributionCLK or External VCO > 1600 MHz................................................... 28 SPI/IC Port Selection ................................................................ 45 Phase-Locked Loop (PLL) .................................................... 30 IC Serial Port Operation .......................................................... 45 2 Configuration of the PLL ...................................................... 30 I C Bus Characteristics .......................................................... 45 Phase Frequency Detector (PFD) ........................................ 30 Data Transfer Process ............................................................ 46 Rev. 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