Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs Data Sheet AD9524 FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency: <1 MHz to 1 GHz OSC Start-up frequency accuracy: <100 ppm (determined by VCXO reference accuracy) REFA, AD9524 REFA Zero delay operation OUT0, REFB, PLL1 PLL2 OUT0 Input-to-output edge timing: <150 ps REFB 6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS REF TEST OUT1, OUT1 6 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of period of VCO SCLK/SCL CONTROL output divider OUT4, SDIO/SDA INTERFACE OUT4 Output-to-output skew: <50 ps 2 (SPI AND I C) SDO ZERO Duty-cycle correction for odd divider settings OUT5, DELAY OUT5 Automatic synchronization of all outputs on power-up 6-CLOCK Absolute output jitter: <200 fs at 122.88 MHz EEPROM DISTRIBUTION Integration range: 12 kHz to 20 MHz Distribution phase noise floor: 160 dBc/Hz ZD IN, ZD IN Digital lock detect Figure 1. Nonvolatile EEPROM stores configuration settings SPI- and IC-compatible serial control port GENERAL DESCRIPTION Dual PLL architecture The AD9524 provides a low power, multi-output, clock PLL1 distribution function with low jitter performance, along with an Low bandwidth for reference input clock cleanup with on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to external VCXO 4.0 GHz. Phase detector rate up to 130 MHz The AD9524 is defined to support the clock requirements for Redundant reference inputs long term evolution (LTE) and multicarrier GSM base station Automatic and manual reference switchover modes designs. It relies on an external VCXO to provide the reference Revertive and nonrevertive switching jitter cleanup to achieve the restrictive low phase noise require- Loss of reference detection with holdover mode ments necessary for acceptable data converter SNR performance. Low noise LVCMOS output from VCXO used for RF/IF synthesizers The input receivers, oscillator, and zero delay receiver provide PLL2 both single-ended and differential operation. When connected Phase detector rate of up to 259 MHz to a recovered system reference clock and a VCXO, the device Integrated low noise VCO generates six low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). APPLICATIONS The frequency and phase of one clock output relative to another LTE and multicarrier GSM base stations clock output can be varied by means of a divider phase select Wireless and broadband infrastructure function that serves as a jitter-free coarse timing adjustment in Medical instrumentation increments that are equal to one-half the period of the signal Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs coming out of the VCO. Low jitter, low phase noise clock distribution An in-package EEPROM can be programmed through the serial Clock generation and translation for SONET, 10Ge, 10G FC, interface to store user defined register settings for power-up and and other 10 Gbps protocols chip reset. Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 09081-001AD9524 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 18 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 19 Functional Block Diagram .............................................................. 1 Detailed Block Diagram ............................................................ 19 General Description ......................................................................... 1 Overview ..................................................................................... 19 Revision History ............................................................................... 3 Component BlocksInput PLL (PLL1) .................................. 20 Specifications ..................................................................................... 4 Component BlocksOutput PLL (PLL2) .............................. 21 Conditions ..................................................................................... 4 Clock Distribution ..................................................................... 23 Supply Current .............................................................................. 4 Zero Delay Operation ................................................................ 25 Power Dissipation ......................................................................... 6 Lock Detect ................................................................................. 25 REFA, REFA, REFB, REFB, OSC IN, OSC IN, and ZD IN, Reset Modes ................................................................................ 26 ZD IN Input Characteristics ...................................................... 6 Power-Down Mode .................................................................... 26 OSC CTRL Output Characteristics .......................................... 7 Serial Control Port ......................................................................... 27 REF TEST Input Characteristics ............................................... 7 SPI/IC Port Selection ................................................................ 27 PLL1 Characteristics .................................................................... 7 IC Serial Port Operation .......................................................... 27 PLL1 Output Characteristics ...................................................... 7 SPI Serial Port Operation .......................................................... 30 Distribution Output Characteristics (OUT0, OUT0 to OUT5, SPI Instruction Word (16 Bits) ................................................. 31 OUT5) ............................................................................................ 8 SPI MSB/LSB First Transfers .................................................... 31 Timing Alignment Characteristics ............................................ 9 EEPROM Operations ..................................................................... 34 Jitter and Noise Characteristics .................................................. 9 Writing to the EEPROM ........................................................... 34 PLL2 Characteristics .................................................................... 9 Reading from the EEPROM ..................................................... 34 PD SYNC RESET Logic Input Pins , , , EEPROM SEL, Programming the EEPROM Buffer Segment ......................... 35 REF SEL ...................................................................................... 10 Power Dissipation and Thermal Considerations ....................... 37 Status Output PinsSTATUS1, STATUS0 ............................. 10 Clock Speed and Driver Mode ................................................. 37 Serial Control PortSPI Mode ................................................ 10 Evaluation of Operating Conditions ........................................ 37 Serial Control PortIC Mode ................................................ 11 Thermally Enhanced Package Mounting Guidelines ............ 38 Absolute Maximum Ratings .......................................................... 12 Control Registers ............................................................................ 39 Thermal Resistance .................................................................... 12 Control Register Map ................................................................ 39 ESD Caution ................................................................................ 12 Control Register Map Bit Descriptions ................................... 43 Pin Configuration and Function Descriptions ........................... 13 Outline Dimensions ....................................................................... 56 Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 56 Input/Output Termination Recommendations .......................... 17 Rev. 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