Low Jitter Clock Generator with Eight LVPECL Outputs Data Sheet AD9525 FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated ultralow noise synthesizer REFA AD9525 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC REFA output or 2 CMOS SYNC outputs REFB SYNC OUT S PLL 2 differential reference inputs and 1 single-ended reference REFB SYNC OUT input OUT7 REFC OUT7 APPLICATIONS OUT6 LTE and multicarrier GSM base stations OUT6 Clocking high speed ADCs, DACs OUT5 ATE and high performance instrumentation OUT5 40/100 Gb/sec OTN line side clocking OUT4 CLKIN Cable/DOCSIS CMTS clocking DIVIDERS OUT4 CLKIN Test and measurement OUT3 OUT3 OUT2 OUT2 OUT1 OUT1 SPI CONTROL OUT0 OUT0 Figure 1. GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements The AD9525 offers a dedicated output that can be used to provide for long-term evolution (LTE) and multicarrier GSM base station a programmable signal for resetting or synchronizing a data designs. converter. The output signal is activated by a SPI write. The AD9525 provides a low power, multioutput, clock distribution The AD9525 is available in a 48-lead LFCSP and can be operated function with low jitter performance, along with an on-chip PLL from a single 3.3 V supply. The external VCXO or VCO can that can be used with an external VCO or VCXO. The VCO input have an operating voltage of up to 5.5 V. and eight LVPECL outputs can operate up to a frequency of The AD9525 operates over the extended industrial temperature 3.6 GHz. All outputs share a common divider that can provide range of 40C to +85C. a division of 1 to 6. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 10011-001AD9525 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 12 Applications ....................................................................................... 1 Thermal Resistance .................................................................... 12 Functional Block Diagram .............................................................. 1 ESD Caution................................................................................ 12 General Description ......................................................................... 1 Pin Configuration and Function Descriptions ........................... 13 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 15 Specifications ..................................................................................... 3 Terminology .................................................................................... 18 Conditions ..................................................................................... 3 Detailed Block Diagram ................................................................ 19 Supply Current .............................................................................. 3 Theory of Operation ...................................................................... 20 Power Dissipation ......................................................................... 3 Configuration of the PLL .......................................................... 20 REFA and REFB Input Characteristics ...................................... 4 Clock Distribution ..................................................................... 23 REFC Input Characteristics ........................................................ 4 SYNC OUT ................................................................................ 23 Clock Inputs .................................................................................. 5 Reset Modes ................................................................................ 25 PLL Characteristics ...................................................................... 5 Power-Down Modes .................................................................. 26 PLL Digital Lock Detect .............................................................. 6 Serial Control Port ......................................................................... 27 Clock Outputs ............................................................................... 6 Pin Descriptions ......................................................................... 27 Timing Characteristics ................................................................ 7 General Operation of Serial Control Port ............................... 27 Clock Output Absolute Time Jitter (Clock Generation The Instruction Word (16 Bits) ................................................ 28 Using External 122.88 MHz VCXO).......................................... 8 MSB/LSB First Transfers ........................................................... 28 Clock Output Absolute Time Jitter (Clock Generation Control Registers ............................................................................ 31 Using External 1475 MHz VCO) ............................................... 8 Control Register Map Overview .............................................. 31 Clock Output Absolute Time Jitter (Clock Generation Register Map Descriptions ............................................................ 33 Using External 2.05 GHz VCO) ................................................. 9 Applications Information .............................................................. 45 Clock Output Absolute Time Jitter (Clock Generation Frequency Planning Using the AD9525 .................................. 45 Using External 3 GHz VCO) ...................................................... 9 Using the AD9525 Outputs for ADC Clock Applications .... 45 Clock Output Additive Phase Noise (Distribution Only Clock Input to Distribution Output, Including VCO LVPECL Clock Distribution ..................................................... 46 Divider) .......................................................................................... 9 SYNC OUT Distribution ......................................................... 46 PD RESET , , and REF SEL Pins ................................................ 10 Outline Dimensions ....................................................................... 47 STATUS and REF MON Pins .................................................. 10 Ordering Guide ............................................................................... 47 Serial Control Port ..................................................................... 11 REVISION HISTORY 4/13Rev. 0 to Rev. A Change to Register 0x000, Bit 6, Table 28 .................................... 33 Changes to Table 35 ........................................................................ 38 Changes to One Channel, One Driver and One Channel, Two Changes to Table 38 ........................................................................ 40 Drivers Parameters, Table 3 .............................................................. 4 Change to Figure 18 ........................................................................ 19 10/12Revision 0: Initial Version Changes to Register 0x01A, Table 28 ............................................ 31 Rev. A Page 2 of 48