Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner Data Sheet AD9544 FEATURES APPLICATIONS Dual DPLL synchronizes 1 Hz to 750 MHz physical layer SyncE and GPS synchronization and jitter cleanup clocks providing frequency translation with jitter cleaning Optical transport networks (OTN), SDH, and macro and small of noisy references cell base stations Complies with ITU-T G.8262 and Telcordia GR-253 OTN mapping/demapping with jitter cleaning Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, Small base station clocking, including baseband and radio G.824, and G.825 Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter Continuous frequency monitoring and reference validation cleanup, and phase transient control for frequency deviation as low as 50 ppb JESD204B support for analog-to-digital converter (ADC) and Both DPLLs feature a 24-bit fractional divider with 24-bit digital-to-analog converter (DAC) clocking programmable modulus Cable infrastructures 4 Programmable digital loop filter bandwidth: 10 Hz to 1850 Hz Carrier Ethernet Automatic and manual holdover and reference switchover, GENERAL DESCRIPTION providing zero delay, hitless, or phase buildout operation The 10 clock outputs of the AD9544 are synchronized to any Programmable priority-based reference switching with one of up to four input references. The digital phase-locked manual, automatic revertive, and automatic nonrevertive loops (DPLLs) reduce timing jitter associated with the external modes supported references. The digitally controlled loop and holdover circuitry 5 pairs of clock output pins with each pair useable as continuously generate a low jitter output signal, even when all differential LVDS/HCSL/CML or as 2 single-ended outputs reference inputs fail. (1 Hz to 500 MHz) 2 differential or 4 single-ended input references The AD9544 is available in a 48-lead LFCSP (7 mm 7 mm) Crosspoint mux interconnects reference inputs to PLLs package and operates over the 40C to +85C temperature Supports embedded (modulated) input/output clock signals range. Fast DPLL locking modes Note that throughout this data sheet, multifunction pins, such Provides internal capability to combine the low phase noise as SDO/M5, are referred to either by the entire pin name or by a of a crystal resonator or crystal oscillator with the single function of the pin, for example, M5, when only that frequency stability and accuracy of a TCXO or OCXO function is relevant. External EEPROM support for autonomous initialization Single 1.8 V power supply operation with internal regulation Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9544 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 System Clock PLL ........................................................................... 30 Applications ....................................................................................... 1 System Clock Input Frequency Declaration ........................... 30 General Description ......................................................................... 1 System Clock Source .................................................................. 30 Revision History ............................................................................... 3 2 Frequency Multiplier ............................................................ 31 Functional Block Diagram .............................................................. 4 Prescale Divider .......................................................................... 31 Specifications ..................................................................................... 5 Feedback Divider ........................................................................ 31 Supply Voltage ............................................................................... 5 System Clock PLL Output Frequency ..................................... 31 Supply Current .............................................................................. 5 System Clock PLL Lock Detector............................................. 31 Power Dissipation ......................................................................... 5 System Clock Stability Timer .................................................... 31 System Clock Inputs, XOA and XOB ......................................... 6 System Clock Input Termination Recommendations ........... 31 Reference Inputs ........................................................................... 7 Digital PLL (DPLL) ........................................................................ 32 Reference Monitors ...................................................................... 8 Overview ..................................................................................... 32 DPLL Phase Characteristics ........................................................ 8 DPLL Phase/Frequency Lock Detectors ................................. 32 Distribution Clock Outputs ........................................................ 9 DPLL Loop Controller ............................................................... 32 Time Duration of Digital Functions ........................................ 10 Applications Information .............................................................. 33 Digital PLL (DPLL0, DPLL1) Specifications .......................... 10 Optical Networking Line Card ................................................. 33 Digital PLL Lock Detection Specifications ............................. 11 Small Cell Base Station .............................................................. 34 Holdover Specifications ............................................................. 11 Initialization Sequence ................................................................... 35 Analog PLL (APLL0, APLL1) Specifications .......................... 11 Status and Control Pins ................................................................. 38 Output Channel Divider Specifications .................................. 11 Multifunction Pins at Reset/Power-Up ................................... 39 System Clock Compensation Specifications ........................... 12 Status Functionality.................................................................... 39 Temperature Sensor Specifications .......................................... 12 Control Functionality ................................................................ 39 Serial Port Specifications ........................................................... 12 Interrupt Request (IRQ) ................................................................ 44 Logic Input Specifications (RESETB, M0 to M6) .................. 14 IRQ Monitor ............................................................................... 44 Logic Output Specifications (M0 to M6) ................................ 14 IRQ Mask..................................................................................... 44 Jitter Generation (Random Jitter) ............................................ 14 IRQ Clear ..................................................................................... 44 Phase Noise ................................................................................. 15 Watchdog Timer ............................................................................. 46 Absolute Maximum Ratings .......................................................... 19 Lock Detectors ................................................................................ 47 Thermal Resistance .................................................................... 19 DPLL Lock Detectors ................................................................ 47 ESD Caution ................................................................................ 19 Phase Step Detector ........................................................................ 49 Pin Configuration and Function Descriptions ........................... 20 Phase Step Limit ......................................................................... 49 Typical Performance Characteristics ........................................... 22 Skew Adjustment ........................................................................ 50 Terminology .................................................................................... 26 EEPROM Usage .............................................................................. 51 Theory of Operation ...................................................................... 27 Overview ..................................................................................... 51 Overview ...................................................................................... 27 EEPROM Controller General Operation ................................ 51 Reference Input Physical Connections .................................... 27 EEPROM Instruction Set .......................................................... 52 Input/Output Termination Recommendations .......................... 28 Multidevice Support .................................................................. 54 System Clock Inputs ................................................................... 28 Serial Control Port ......................................................................... 56 Reference Clock Inputs .............................................................. 28 SPI/IC Port Selection ................................................................ 56 Clock Outputs ............................................................................. 29 SPI Serial Port Operation .......................................................... 56 Rev. 0 Page 2 of 62