Quad/Octal Input Network Clock Generator/Synchronizer Data Sheet AD9548 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Network synchronization Supports reference switchover with phase build-out Cleanup of reference clock jitter Supports hitless reference switchover GPS 1 pulse per second synchronization Auto/manual holdover and reference switchover SONET/SDH clocks up to OC-192, including FEC 4 pairs of reference input pins with each pair configurable as Stratum 2 holdover, jitter cleanup, and phase transient a single differential input or as 2 independent single- control ended inputs Stratum 3E and Stratum 3 reference clocks Input reference frequencies from 1 Hz to 750 MHz Wireless base station controllers Reference validation and frequency monitoring (1 ppm) Cable infrastructure Programmable input reference switchover priority Data communications 30-bit programmable input reference divider GENERAL DESCRIPTION 4 pairs of clock output pins with each pair configurable as a The AD9548 provides synchronization for many systems, single differential LVDS/LVPECL output or as 2 single- including synchronous optical networks (SONET/SDH). The ended CMOS outputs AD9548 generates an output clock synchronized to one of up to Output frequencies up to 450 MHz four differential or eight single-ended external input references. 30-bit integer and 10-bit fractional programmable feedback The digital PLL allows for reduction of input time jitter or phase divider noise associated with the external references. The AD9548 Programmable digital loop filter covering loop bandwidths continuously generates a clean (low jitter), valid output clock from 0.001 Hz to 100 kHz even when all references have failed by means of a digitally Optional low noise LC-VCO system clock multiplier controlled loop and holdover circuitry. Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles The AD9548 operates over an industrial temperature range of Software controlled power-down 40C to +85C. 88-lead LFCSP package FUNCTIONAL BLOCK DIAGRAM STABLE ANALOG SOURCE FILTER AD9548 CLOCK DISTRIBUTION CLOCK MULTIPLIER CHANNEL 0 DIVIDER CHANNEL 1 DIVIDER DIGITAL CHANNEL 2 DAC PLL DIVIDER REFERENCE INPUTS CHANNEL 3 AND DIVIDER MONITOR MUX SYNC SERIAL CONTROL INTERFACE STATUS AND EEPROM 2 (SPI or I C) CONTROL PINS Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08022-001AD9548 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 32 Applications ....................................................................................... 1 Direct Digital Synthesizer ......................................................... 34 General Description ......................................................................... 1 Tuning Word Processing ........................................................... 35 Functional Block Diagram .............................................................. 1 Loop Control State Machine ..................................................... 36 Revision History ............................................................................... 3 System Clock Inputs ................................................................... 37 Specif icat ions ..................................................................................... 4 SYSCLK PLL Multiplier ............................................................. 38 Supply Voltage ............................................................................... 4 Clock Distribution ..................................................................... 40 Supply Current .............................................................................. 4 Status and Control .......................................................................... 44 Power Dissipation ......................................................................... 4 Multifunction Pins (M0 to M7) ............................................... 44 Logic Inputs (M7 to M0, RESET, TDI, TCLK, TMS) .............. 5 IRQ Pin ........................................................................................ 45 Logic Outputs (M7 to M0, IRQ, TDO) ..................................... 5 Watchdog Timer ......................................................................... 46 System Clock Inputs (SYSCLKP/SYSCLKN) ........................... 5 EEPROM ..................................................................................... 46 Distribution Clock Inputs (CLKINP/CLKINN) ...................... 6 Serial Control Port ......................................................................... 51 Reference Inputs (REFA/REFAA to REFD/REFDD) .............. 7 SPI/I2C Port Selection ................................................................ 51 Reference Monitors ...................................................................... 7 SPI Serial Port Operation .......................................................... 51 Reference Switchover Specifications .......................................... 8 I2C Serial Port Operation .......................................................... 56 Distribution Clock Outputs (OUT0 to OUT3) ........................ 8 Input/Output Programming Registers ........................................ 59 DAC Output Characteristics (DACOUTP/DACOUTN) ....... 9 Buffered/Active Registers .......................................................... 59 Time Duration of Digital Functions ........................................ 10 Autoclear Registers ...................................................................... 59 Digital PLL .................................................................................. 10 Register Access Restrictions ........................................................ 59 Digital PLL Lock Detection ...................................................... 10 Register Map ................................................................................... 60 Holdover Specifications ............................................................. 10 Register Map Bit Descriptions ...................................................... 70 Serial Port SpecificationsSPI Mode ...................................... 11 Serial Port Configuration (Register 0x0000 to 2 Register 0x0005) ......................................................................... 70 Serial Port SpecificationsI C Mode ...................................... 11 System Clock (Register 0x0100 to Register 0x0108) ............. 71 Jitter Generation ......................................................................... 12 General Configuration (Register 0x0200 to Register 0x0214) .. 72 Absolute Maximum Ratings .......................................................... 14 DPLL Configuration (Register 0x0300 to Register 0x031B) 75 ESD Caution ................................................................................ 14 Clock Distribution Output Configuration (Register 0x0400 to Pin Configuration and Function Descriptions ........................... 15 Register 0x0419) ........................................................................... 77 Typical Performance Characteristics ........................................... 18 Reference Input Configuration (Register 0x0500 to Input/Output Termination Recommendations .......................... 23 Register 0x0507) ......................................................................... 81 Getting Started ................................................................................ 24 Profile Registers (Register 0x0600 to Register 0x07FF) ........ 83 Power-On Reset .......................................................................... 24 Operational Controls (Register 0x0A00 to Register 0x0A10) ... 92 Initial M0 to M7 Pin Programming ......................................... 24 Clock Part Serial ID (Register 0x0C00 to Register 0x0C07) 97 Device Register Programming .................................................. 24 Status Readback (Register 0x0D00 to Register 0x0D19) ...... 97 Theory of Operation ...................................................................... 26 Nonvolatile Memory (EEPROM) Control (Register 0x0E00 to O ver vie w ...................................................................................... 26 Register 0x0E03) ........................................................................ 101 Reference Clock Inputs .............................................................. 27 EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3F) ........................................................................ 101 Reference Monitors .................................................................... 27 Power Supply Partitions ............................................................... 106 Reference Profiles ....................................................................... 28 3.3 V Supplies ............................................................................ 106 Reference Switchover ................................................................. 30 Rev. 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