Oscillator Frequency Upconverter Data Sheet AD9552 FEATURES GENERAL DESCRIPTION Converts a low frequency input reference signal to a high The AD9552 is a fractional-N phase locked loop (PLL) based frequency output signal clock generator designed specifically to replace high frequency Input frequencies from 6.6 MHz to 112.5 MHz crystal oscillators and resonators. The device employs a sigma- Output frequencies up to 900 MHz delta (-) modulator (SDM) to accommodate fractional Preset pin programmable frequency translation ratios frequency synthesis. The user supplies an input reference signal Arbitrary frequency translation ratios via SPI port by connecting a single-ended clock signal directly to the REF On-chip VCO pin or by connecting a crystal resonator across the XTAL pins. Accepts a crystal resonator and/or an external oscillator The AD9552 is pin programmable, providing one of 64 standard as a reference frequency source output frequencies based on one of eight common input Secondary output (either integer-related to the primary frequencies. The device also has a 3-wire SPI interface, enabling output or a copy of the reference input) the user to program custom input-to-output frequency ratios. RMS jitter: <0.5 ps The AD9552 relies on an external capacitor to complete the loop SPI-compatible, 3-wire programming interface filter of the PLL. The output is compatible with LVPECL, LVDS, Single supply (3.3 V) or single-ended CMOS logic levels, although the AD9552 is Very low power: <400 mW (under most conditions) implemented in a strictly CMOS process. Small package size (5 mm 5 mm) The AD9552 is specified to operate over the extended industrial APPLICATIONS temperature range of 40C to +85C. Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC), 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSIS High-definition video frequency translation Wireless infrastructure Test and measurement (including handheld devices) BASIC BLOCK DIAGRAM AD9552 OUT2 INPUT REF FREQUENCY OUTPUT PLL SOURCE CIRCUITRY OUT1 XTAL SELECTOR PIN-DEFINED AND SERIAL PROGRAMMING Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092012 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07806-001AD9552 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Preset Frequency Ratios ............................................................ 13 Applications ....................................................................................... 1 Component Blocks ..................................................................... 15 General Description ......................................................................... 1 Part Initialization and Automatic Power-On Reset ............... 17 Basic Block Diagram ........................................................................ 1 Output/Input Frequency Relationship .................................... 17 Revision History ............................................................................... 2 Calculating Divider Values ....................................................... 17 Specifications ..................................................................................... 3 Low Dropout (LDO) Regulators .............................................. 18 Crystal Input Characteristics ...................................................... 4 Applications Information .............................................................. 19 Output Characteristics ................................................................. 4 Thermal Performance ................................................................ 19 Jitter Characteristics ..................................................................... 5 Serial Control Port ......................................................................... 20 Serial Control Port ....................................................................... 6 Serial Control Port Pin Descriptions ....................................... 20 Serial Control Port Timing ......................................................... 6 Operation of the Serial Control Port ....................................... 20 Absolute Maximum Ratings ............................................................ 7 Instruction Word (16 Bits) ........................................................ 21 ESD Caution .................................................................................. 7 MSB/LSB First Transfers ........................................................... 21 Pin Configuration and Function Descriptions ............................. 8 Register Map ................................................................................... 23 Typical Performance Characteristics ............................................. 9 Register Map Descriptions ........................................................ 24 Input/Output Termination Recommendations .......................... 12 Outline Dimensions ....................................................................... 30 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 30 REVISION HISTORY 11/12Rev. D to Rev. E Moved Preset Frequency Ratios Section ..................................... 13 Changes to Component Blocks Section ...................................... 15 Changes to Figure 2 ........................................................................... 8 Added Part Initialization and Automatic Power-On Changes to Serial Control Port Section ........................................ 20 Reset Section ................................................................................... 17 Changes to Table 17 ......................................................................... 24 Changes to Table 18 ......................................................................... 25 4/10Rev. A to Rev. B Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) ...... 31 Changes to Preset Frequency Ratios Section .............................. 12 Changes to Ordering Guide ........................................................... 31 Moved Table 15 and Changes to Table 15 ................................... 13 7/11Rev. C to Rev. D Changes to Figure 17 ...................................................................... 14 Changes to PLL Section, Output Dividers Section, and Changes to Table 1, Reference Clock Input Characteristics, Input-to-OUT2 Option Section ............................................... 15 Input High Voltage and Input Low Voltage Parameter Values ... 4 Changes to Output/Input Frequency Relationship Section ...... 16 Changes to Table 8, Added Endnote for Pin 9 and Pin 10 .......... 8 Changes to Table 22 ....................................................................... 23 Changes to Part Initialization Automatic Power-On Reset Changes to Table 26 ....................................................................... 26 Section, Second Paragraph ............................................................ 17 Changes to Thermal Performance Section , First Paragraph ... 19 9/09Rev. 0 to Rev. A Changes to Serial Port Control Section, First Paragraph .......... 20 Changes to Table 4 ............................................................................. 3 Changes to Table 20, Added Endnote to Bit 2 Description ...... 27 Changes to Table 5 ............................................................................. 4 Updated Outline Dimensions ....................................................... 31 Added Table 6 Renumbered Sequentially ..................................... 4 7/10Rev. B to Rev. C Changes to Figure 5 ........................................................................... 9 Changes to PLL Section ................................................................. 14 Changed Crystal Load Capacitance to 15 pF ............. Throughout Changes to Table 22 ....................................................................... 21 Added Conditions Statement to Specifications Section, Supply Changes to Table 25 ....................................................................... 24 Voltage Specifications, and Input Voltage Specifications ............ 3 Reformatted Specifications Section (Renumbered Sequentially) ..... 3 7/09Revision 0: Initial Version Added Input/Output Termination Recommendations Section, Figure 17, and Figure 18 (Renumbered Sequentially) ............... 13 Rev. E Page 2 of 32