Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet AD9554 FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Network synchronization, including synchronous Ethernet Supports smooth reference switchover with virtually no and synchronous digital hierarchy (SDH) to optical disturbance on output phase transport network (OTN) mapping/demapping Supports Telcordia GR-253 jitter generation, transfer, and Cleanup of reference clock jitter tolerance for SONET/SDH up to OC-192 systems SONET/SDH clocks up to OC-192, including FEC Supports ITU-T G.8262 synchronous Ethernet slave clocks Stratum 3 holdover, jitter cleanup, and phase transient Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and control ITU-T G.8261 Cable infrastructure Auto/manual holdover and reference switchover Data communications Adaptive clocking allows dynamic adjustment of feedback Professional video dividers for use in OTN mapping/demapping applications GENERAL DESCRIPTION Quad digital phase-locked loop (DPLL) architecture with four The AD9554 is a low loop bandwidth clock translator that reference inputs (single-ended or differential) provides jitter cleanup and synchronization for many systems, 4 4 crosspoint allows any reference input to drive any PLL including synchronous optical networks (SONET/SDH). The Input reference frequencies from 2 kHz to 1000 MHz AD9554 generates an output clock synchronized to up to four Reference validation and frequency monitoring: 2 ppm external input references. The digital PLL (DPLL) allows for Programmable input reference switchover priority reduction of input time jitter or phase noise associated with the 20-bit programmable input reference divider external references. The digitally controlled loop and holdover 8 differential clock outputs with each differential pair circuitry of the AD9554 continuously generates a low jitter configurable as HCSL, LVDS-compatible, or LVPECL- output clock even when all reference inputs have failed. compatible Output frequency range: 430 kHz to 941 MHz The AD9554 operates over an industrial temperature range of Programmable 18-bit integer and 24-bit fractional feedback 40C to +85C. If a smaller device is needed, the AD9554-1 is divider in digital PLL a version of this device with one output per PLL. If a single or Programmable loop bandwidths from 0.1 Hz to 4 kHz dual DPLL version of this device is needed, refer to the AD9557 Optional off-chip EEPROM to store power-up profile or AD9559, respectively. 72-lead (10 mm 10 mm) LFCSP package FUNCTIONAL BLOCK DIAGRAM EXTERNAL Q0 A DIVIDER SERIAL INTERFACE STATUS AND EEPROM 2 (SPI OR I C) CONTROL PINS (OPTIONAL) P0 DIVIDER Q0 B DIVIDER DIGITAL ANALOG Q1 A DIVIDER PLL 0 PLL 0 P1 DIVIDER Q1 B DIVIDER DIGITAL ANALOG REFERENCE PLL 1 PLL 1 INPUT MONITOR Q2 A DIVIDER AND MUX DIGITAL ANALOG P2 DIVIDER PLL 2 PLL 2 Q2 B DIVIDER DIGITAL ANALOG PLL 3 PLL 3 P3 DIVIDER Q3 A DIVIDER STABLE CLOCK Q3 B DIVIDER SOURCE MULTIPLIER AD9554 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12132-001AD9554 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 35 Applications ....................................................................................... 1 Loop Control State Machine ..................................................... 38 General Description ......................................................................... 1 System Clock (SYSCLK) ................................................................ 39 Functional Block Diagram .............................................................. 1 SYSCLK Inputs ........................................................................... 39 Revision History ............................................................................... 4 SYSCLK Multiplier ..................................................................... 39 Specif icat ions ..................................................................................... 5 Output Analog PLL (APLL) .......................................................... 41 Supply Voltage ............................................................................... 5 APLL Configuration .................................................................. 41 Supply Current .............................................................................. 5 APLL Calibration ....................................................................... 41 Power Dissipation ......................................................................... 6 Clock Distribution .......................................................................... 42 System Clock Inputs (XOA, XOB) ............................................. 6 Clock Dividers ............................................................................ 42 Reference Inputs ........................................................................... 7 Output Amplitude and Power-Down ...................................... 42 Reference Monitors ...................................................................... 8 Clock Distribution Synchronization ........................................ 43 Reference Switchover Specifications .......................................... 8 Status and Control .......................................................................... 44 Distribution Clock Outputs ........................................................ 9 Multifunction Pins (M0 to M9) ............................................... 44 Time Duration of Digital Functions ........................................ 11 IRQ Function .............................................................................. 44 Digital PLL (DPLL 0, DPLL 1, DPLL 2, and DPLL 3) ...... 11 Watchdog Timer ......................................................................... 45 Analog PLL (APLL 0, APLL 1, APLL 2, and APLL 3) ...... 11 EEPROM ..................................................................................... 45 Digital PLL Lock Detection ...................................................... 12 Serial Control Port ......................................................................... 49 Holdover Specifications ............................................................. 12 SPI/I2C Port Selection ................................................................ 49 Serial Port SpecificationsSerial Port Interface (SPI) Mode12 SPI Serial Port Operation .......................................................... 49 2 Serial Port SpecificationsI C Mode ...................................... 13 I2C Serial Port Operation .......................................................... 52 RESET Programming the Input/Output Registers .................................. 55 Logic Inputs ( , M9 to M0) ............................................. 14 Buffered/Active Registers .......................................................... 55 Logic Outputs (M9 to M0) ........................................................ 14 Write Detect Registers ............................................................... 55 Jitter Generation ......................................................................... 15 Autoclear Registers ..................................................................... 55 Absolute Maximum Ratings .......................................................... 16 Register Access Restrictions ...................................................... 55 ESD Caution ................................................................................ 16 Thermal Performance .................................................................... 56 Pin Configuration and Function Descriptions ........................... 17 Power Supply Partitions ................................................................. 57 Typical Performance Characteristics ........................................... 21 VDD Supplies ............................................................................. 57 Input/Output Termination Recommendations .......................... 24 VDD SP Supply ......................................................................... 57 Getting Started ................................................................................ 25 Register Map ................................................................................... 58 Chip Power Monitor and Startup ............................................. 25 Register Map Bit Descriptions ...................................................... 70 Multifunction Pins at Reset/Power-Up ................................... 25 Serial Control Port Configuration (Register 0x0000 to Device Register Programming Using a Register Setup File .. 25 Register 0x0001) ......................................................................... 70 Register Programming Overview ............................................. 30 Clock Part Family ID (Register 0x0003 to Register 0x0006) 71 Theory of Operation ...................................................................... 33 SPI Version (Register 0x000B) .................................................. 71 O ver vie w ...................................................................................... 33 Vendor ID (Register 0x000C to Register 0x000D) ................ 71 Reference Input Physical Connections .................................... 34 IO Update (Register 0x000F) ................................................... 71 Reference Monitors .................................................................... 34 User Scratchpad (Register 0x00FE to Register 0x00FF) ....... 71 Reference Input Block ................................................................ 34 Reference Switchover ................................................................. 35 Rev. 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