Dual Input Multiservice Line Card Adaptive Clock Translator Data Sheet AD9557 FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Network synchronization, including synchronous Ethernet Supports smooth reference switchover with virtually and SDH to OTN mapping/demapping no disturbance on output phase Cleanup of reference clock jitter Supports Telcordia GR-253 jitter generation, transfer, and SONET/SDH/OTN clocks up to 100 Gbps, including FEC tolerance for SONET/SDH up to OC-192 systems Stratum 3 holdover, jitter cleanup, and phase transient control Supports ITU-T G.8262 synchronous Ethernet slave clocks Wireless base station controllers Supports ITU-T G.823, G.824, G.825, and G.8261 Cable infrastructure Auto/manual holdover and reference switchover Data communications 2 reference inputs (single-ended or differential) GENERAL DESCRIPTION Input reference frequencies: 2 kHz to 1250 MHz The AD9557 is a low loop bandwidth clock multiplier that Reference validation and frequency monitoring (1 ppm) provides jitter cleanup and synchronization for many systems, Programmable input reference switchover priority including synchronous optical networks (OTN/SONET/SDH). 20-bit programmable input reference divider The AD9557 generates an output clock synchronized to up to 2 pairs of clock output pins, with each pair configurable as four external input references. The digital PLL allows for a single differential LVDS/HSTL output or as 2 single-ended reduction of input time jitter or phase noise associated with CMOS outputs the external references. The digitally controlled loop and Output frequencies: 360 kHz to 1250 MHz holdover circuitry of the AD9557 continuously generates a low Programmable 17-bit integer and 23-bit fractional jitter output clock even when all reference inputs have failed. feedback divider in digital PLL Programmable digital loop filter covering loop bandwidths The AD9557 operates over an industrial temperature range from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking) of 40C to +85C. If more inputs/outputs are needed, refer to Low noise system clock multiplier the AD9558 for the four-input/six-output version of the same Frame sync support device. Adaptive clocking Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles Pin program function for easy frequency translation configuration Software controlled power-down 40-lead, 6 mm 6 mm, LFCSP package FUNCTIONAL BLOCK DIAGRAM AD9557 3 TO 11 CHANNEL 0 HF DIVIDER 0 DIVIDER REFERENCE INPUT DIGITAL ANALOG AND PLL PLL MONITOR MUX 3 TO 11 CHANNEL 1 HF DIVIDER 1 DIVIDER CLOCK SERIAL INTERFACE STATUS AND EEPROM MULTIPLIER 2 (SPI OR I C) CONTROL PINS STABLE SOURCE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09197-001AD9557 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Loop Control State Machine ..................................................... 34 Applications ....................................................................................... 1 System Clock (SYSCLK) ................................................................ 35 General Description ......................................................................... 1 System Clock Inputs................................................................... 35 Functional Block Diagram .............................................................. 1 SYStem Clock Multiplier ........................................................... 35 Revision History ............................................................................... 3 Output PLL (APLL) ....................................................................... 37 Specifications ..................................................................................... 5 Clock Distribution .......................................................................... 38 Supply Voltage ............................................................................... 5 Output Power-Down ................................................................. 38 Supply Current .............................................................................. 5 Output Enable ............................................................................. 38 Power Dissipation ......................................................................... 6 Output Mode .............................................................................. 38 Logic Inputs (RESET, SYNC, PINCONTROL, M3 to M0) .... 6 Clock Distribution Synchronization ........................................ 38 Status and Control .......................................................................... 40 Logic Outputs (M3 to M0, IRQ) ................................................ 7 Multifunction Pins (M3 to M0) ............................................... 40 System Clock Inputs (XOA, XOB) ............................................. 7 IRQ Pin ........................................................................................ 40 Reference Inputs ........................................................................... 8 Watchdog Timer ......................................................................... 41 Reference Monitors ...................................................................... 9 EEPROM ..................................................................................... 41 Reference Switchover Specifications .......................................... 9 Serial Control Port ......................................................................... 47 Distribution Clock Outputs ...................................................... 10 SPI/IC Port Selection ................................................................ 47 Time Duration of Digital Functions ........................................ 11 SPI Serial Port Operation .......................................................... 47 Digital PLL .................................................................................. 12 2 I C Serial Port Operation .......................................................... 51 Digital PLL Lock Detection ...................................................... 12 Programming the I/O Registers ................................................... 54 Holdover Specifications ............................................................. 12 Buffered/Active Registers .......................................................... 54 Serial Port SpecificationsSPI Mode ...................................... 13 2 Autoclear Registers ..................................................................... 54 Serial Port SpecificationsI C Mode ...................................... 14 Register Access Restrictions...................................................... 54 Jitter Generation ......................................................................... 14 Thermal Performance .................................................................... 55 Absolute Maximum Ratings .......................................................... 17 Power Supply Partitions ................................................................. 56 ESD Caution ................................................................................ 17 Recommended Configuration for 3.3 V Switching Supply ..... 56 Pin Configuration and Function Descriptions ........................... 18 Configuration for 1.8 V Supply ................................................ 56 Typical Performance Characteristics ........................................... 20 Pin Program Function Description ............................................. 57 Input/Output Termination Recommendations .......................... 25 Overview of On-Chip ROM Features ..................................... 57 Getting Started ................................................................................ 26 Hard Pin Programming Mode.................................................. 58 Chip Power Monitor and Startup ............................................. 26 Soft Pin Programming Mode Overview ................................. 58 Multifunction Pins at Reset/Power-Up ................................... 26 Register Map ................................................................................... 59 Device Register Programming Using a Register Setup File ..... 26 Register Map Bit Descriptions ...................................................... 68 Register Programming Overview ............................................. 27 Serial Port Configuration (Register 0x0000 to Theory of Operation ...................................................................... 30 Register 0x0005) ......................................................................... 68 Overview ...................................................................................... 30 Silicon Revision (Register 0x000A) ......................................... 68 Reference Clock Inputs .............................................................. 31 Clock Part Serial ID (Register 0x000C to Reference Monitors .................................................................... 31 Register 0x000D) ........................................................................ 68 Reference Profiles ....................................................................... 31 System Clock (Register 0x0100 to Register 0x0108) ............. 69 Reference Switchover ................................................................. 31 General Configuration (Register 0x0200 to Digital PLL (DPLL) Core .......................................................... 32 Register 0x0214) ......................................................................... 70 Rev. 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