Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet AD9559 FEATURES Pin program function for easy frequency translation configuration Supports GR-1244 Stratum 3 stability in holdover mode Software controlled power-down Supports smooth reference switchover with virtually 72-lead (10 mm 10 mm) LFCSP package no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and APPLICATIONS tolerance for SONET/SDH up to OC-192 systems Network synchronization, including synchronous Ethernet Supports ITU-T G.8262 synchronous Ethernet slave clocks and SDH to OTN mapping/demapping Supports ITU-T G.823, G.824, G.825, and G.8261 Cleanup of reference clock jitter Auto/manual holdover and reference switchover SONET/SDH clocks up to OC-192, including FEC Adaptive clocking allows dynamic adjustment of feedback Stratum 3 holdover, jitter cleanup, and phase transient dividers for use in OTN mapping/demapping applications control Dual digital PLL architecture with four reference inputs Wireless base station controllers (single-ended or differential) Cable infrastructure 4x2 crosspoint allows any reference input to drive either PLL Data communications Input reference frequencies from 2 kHz to 1250 MHz Reference validation and frequency monitoring (2 ppm) GENERAL DESCRIPTION Programmable input reference switchover priority The AD9559 is a low loop bandwidth clock multiplier that 20-bit programmable input reference divider provides jitter cleanup and synchronization for many systems, 4 pairs of clock output pins with each pair configurable as a including synchronous optical networks (SONET/SDH). The single differential LVDS/HSTL output or as 2 single-ended AD9559 generates an output clock synchronized to up to four CMOS outputs external input references. The digital PLL allows for reduction Output frequencies: 262 kHz to 1250 MHz of input time jitter or phase noise associated with the external Programmable 17-bit integer and 23-bit fractional references. The digitally controlled loop and holdover circuitry feedback divider in digital PLL of the AD9559 continuously generates a low jitter output clock Programmable digital loop filter covering loop bandwidths even when all reference inputs have failed. from 0.1 Hz to 2 kHz The AD9559 operates over an industrial temperature range of Low noise system clock multiplier 40C to +85C. If a single DPLL version of this part is needed, Optional crystal resonator for system clock input refer to the AD9557. On-chip EEPROM to store multiple power-up profiles FUNCTIONAL BLOCK DIAGRAM CHANNEL 0A AD9559 DIVIDER DIGITAL ANALOG 3 TO 11 CHANNEL 0B PLL 0 PLL 0 HF DIVIDER 0 DIVIDER REFERENCE INPUT DIGITAL ANALOG 3 TO 11 CHANNEL 1A MONITOR PLL 1 PLL 1 HF DIVIDER 1 DIVIDER AND MUX CLOCK EEPROM CHANNEL 1B STATUS AND MULTIPLIER SERIAL INTERFACE DIVIDER CONTROL PINS 2 (SPI OR I C) STABLE SOURCE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 10644-001AD9559 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 34 Applications ....................................................................................... 1 Loop Control State Machine ..................................................... 36 General Description ......................................................................... 1 System Clock (SYSCLK) ................................................................ 37 Functional Block Diagram .............................................................. 1 SYSCLK Inputs ........................................................................... 37 Revision History ............................................................................... 3 SYSCLK Multiplier ..................................................................... 37 Specifications ..................................................................................... 4 Output PLL (APLL) ....................................................................... 39 Supply Voltage ............................................................................... 4 APLL Configuration .................................................................. 39 Supply Current .............................................................................. 4 APLL Calibration ....................................................................... 39 Power Dissipation ......................................................................... 5 Clock Distribution .......................................................................... 40 System Clock Inputs (XOA, XOB) ............................................. 5 Clock Dividers ............................................................................ 40 Reference Inputs ........................................................................... 6 Output Enable ............................................................................. 40 Reference Monitors ...................................................................... 7 Output Mode and Power-Down .............................................. 40 Reference Switchover Specifications .......................................... 7 Clock Distribution Synchronization ........................................ 41 Distribution Clock Outputs ........................................................ 8 Status and Control .......................................................................... 42 Time Duration of Digital Functions ........................................ 10 Multifunction Pins (M0 to M5) ............................................... 42 Digital PLL (DPLL 0 and DPLL 1) ........................................ 10 IRQ Function .............................................................................. 42 Analog PLL (APLL 0 and APLL 1) ........................................ 10 Watchdog Timer ......................................................................... 43 Digital PLL Lock Detection ...................................................... 10 EEPROM ..................................................................................... 43 Holdover Specifications ............................................................. 10 Serial Control Port ......................................................................... 49 Serial Port SpecificationsSPI Mode ...................................... 11 SPI/IC Port Selection ................................................................ 49 2 Serial Port SpecificationsI C Mode ...................................... 12 SPI Serial Port Operation .......................................................... 49 RESET IC Serial Port Operation .......................................................... 53 Logic Inputs ( , M5 to M0) ............................................. 12 Programming the I/O Registers ................................................... 56 Logic Outputs (M5 to M0) ........................................................ 12 Buffered/Active Registers .......................................................... 56 Jitter Generation ......................................................................... 13 Write Detect Registers ............................................................... 56 Absolute Maximum Ratings .......................................................... 16 Autoclear Registers ..................................................................... 56 ESD Caution ................................................................................ 16 Register Access Restrictions...................................................... 56 Pin Configuration and Function Descriptions ........................... 17 Thermal Performance .................................................................... 57 Typical Performance Characteristics ........................................... 20 Power Supply Partitions ................................................................. 58 Input/Output Termination Recommendations .......................... 26 3.3 V Supplies .............................................................................. 58 Getting Started ................................................................................ 27 1.8 V Supplies .............................................................................. 58 Chip Power Monitor and Startup ............................................. 27 Bypass Capacitors for Pin 21 and Pin 33 ................................. 58 Multifunction Pins at Reset/Power-Up ................................... 27 Register Map ................................................................................... 59 Device Register Programming Using a Register Setup File .. 27 Register Map Bit Descriptions ...................................................... 72 Register Programming Overview ............................................. 28 Serial Control Port Configuration (Register 0x0000 to Theory of Operation ...................................................................... 31 Register 0x0005) ......................................................................... 72 Overview ...................................................................................... 31 Clock Part Family ID (Register 0x000C and Register 0x000D) 72 Reference Input Physical Connections .................................... 32 User Scratchpad (Register 0x000E and Register 0x000F) ..... 73 Reference Monitors .................................................................... 32 General Configuration (Register 0x0100 to Register 0x0109) .. 73 Reference Input Block ................................................................ 32 IRQ Mask (Register 0x010A to Register 0x112) .................... 74 Reference Switchover ................................................................. 33 Rev. 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