12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9627 FEATURES FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ SNR = 69.4 dBc (70.4 dBFS) to 70 MHz 125 MSPS AVDD DVDD FD(0:3)A DCS DFS CSB DRVDD SFDR = 85 dBc to 70 MHz 125 MSPS Low power: 750 mW 125 MSPS FD BITS/THRESHOLD SPI DETECT SNR = 69.2 dBc (70.2 dBFS) to 70 MHz 150 MSPS D11A SFDR = 84 dBc to 70 MHz 150 MSPS PROGRAMMING DATA D0A VIN+A Low power: 820 mW 150 MSPS SHA ADC 1.8 V analog supply operation VINA SIGNAL CLK+ 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS MONITOR VREF CLK output supply SENSE DIVIDE DCOA Integer 1-to-8 input clock divider 1 TO 8 DCO GENERATION CML IF sampling frequencies to 450 MHz REF DCOB SELECT DUTY CYCLE Internal ADC voltage reference RBIAS D11B STABILIZER Integrated ADC sample-and-hold inputs D0B VINB Flexible analog input range: 1 V p-p to 2 V p-p SHA ADC Differential analog inputs with 650 MHz bandwidth VIN+B SIGNAL MONITOR ADC clock duty cycle stabilizer DATA AD9627 95 dB channel isolation/crosstalk MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR Serial port control SYNC DETECT INTERFACE User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes AGND SYNC FD(0:3)B SMI SMI SMI DRGND SDFS SCLK/ SDO/ Integrated receive features PDWN OEB NOTES Fast detect/threshold bits 1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY SEE FIGURE 7 FOR LVDS PIN NAMES. Composite signal monitor Figure 1. APPLICATIONS Communications PRODUCT HIGHLIGHTS Diversity radio systems 1. Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ Multimode digital receivers (3G) 150 MSPS ADC. GSM, EDGE, WCDMA, 2. Fast overrange detect and signal monitor with serial output. CDMA2000, WiMAX, TD-SCDMA 3. Signal monitor block with dedicated serial output mode. I/Q demodulation systems Smart antenna systems 4. Proprietary differential input that maintains excellent SNR General-purpose software radios performance for input frequencies up to 450 MHz. Broadband data applications 5. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 7. Pin compatibility with the AD9640, AD9627-11, and AD9600 for a simple migration from 12 bits to 14 bits, 11 bits, or 10 bits. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20072010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 06571-001AD9627 TABLE OF CONTENTS Features .............................................................................................. 1 Signal Monitor ................................................................................ 36 Applications ....................................................................................... 1 Peak Detector Mode................................................................... 36 Functional Block Diagram .............................................................. 1 RMS/MS Magnitude Mode ......................................................... 36 Product Highlights ........................................................................... 1 Threshold Crossing Mode ......................................................... 37 Revision History ............................................................................... 3 Additional Control Bits ............................................................. 37 General Description ......................................................................... 4 DC Correction ............................................................................ 37 Specif icat ions ..................................................................................... 5 Signal Monitor SPORT Output ................................................ 38 ADC DC SpecificationsAD9627-80/AD9627-105 .................. 5 Built-In Self-Test (BIST) and Output Test .................................. 39 ADC DC SpecificationsAD9627-125/AD9627-150 ................ 6 Built-In Self-Test (BIST) ............................................................ 39 ADC AC SpecificationsAD9627-80/AD9627-105 ................... 7 Output Test Modes ..................................................................... 39 ADC AC SpecificationsAD9627-125/AD9627-150 ................. 8 Channel/Chip Synchronization .................................................... 40 Digital Specifications ................................................................... 9 Serial Port Interface (SPI) .............................................................. 41 Switching SpecificationsAD9627-80/AD9627-105 ................ 11 Configuration Using the SPI ..................................................... 41 Switching SpecificationsAD9627-125/AD9627-150 .............. 12 Hardware Interface ..................................................................... 41 Timing Specifications ................................................................ 13 Configuration Without the SPI ................................................ 42 Absolute Maximum Ratings .......................................................... 15 SPI Accessible Features .............................................................. 42 Thermal Characteristics ............................................................ 15 Memory Map .................................................................................. 43 ESD Caution ................................................................................ 15 Reading the Memory Map Register Table ............................... 43 Pin Configurations and Function Descriptions ......................... 16 Memory Map Register Table ..................................................... 44 Equivalent Circuits ......................................................................... 20 Memory Map Register Descriptions ........................................ 47 Typical Performance Characteristics ........................................... 21 Applications Information .............................................................. 50 Theory of Operation ...................................................................... 26 Design Guidelines ...................................................................... 50 ADC Architecture ...................................................................... 26 Evaluation Board ............................................................................ 51 Analog Input Considerations .................................................... 26 Power Supplies ............................................................................ 51 Voltage Reference ....................................................................... 28 Input Signals................................................................................ 51 Clock Input Considerations ...................................................... 29 Output Signals ............................................................................ 51 Power Dissipation and Standby Mode ..................................... 31 Default Operation and Jumper Selection Settings ................. 52 Digital Outputs ........................................................................... 32 Alternative Clock Configurations ............................................ 52 Timing .......................................................................................... 32 Alternative Analog Input Drive Configuration...................... 53 ADC Overrange and Gain Control .............................................. 33 Schematics ................................................................................... 54 Fast Detect Overview ................................................................. 33 Evaluation Board Layouts ......................................................... 64 ADC Fast Magnitude ................................................................. 33 Bill of Materials ........................................................................... 72 ADC Overrange (OR) ................................................................ 34 Outline Dimensions ....................................................................... 74 Gain Switching ............................................................................ 34 Ordering Guide .......................................................................... 74 Rev. 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