12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9628 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SPI SNR = 71.2 dBFS 70 MHz ORA SFDR = 93 dBc 70 MHz PROGRAMMING DATA D11A VIN+A Low power: 101 mW/channel 125 MSPS ADC Differential analog input with 650 MHz bandwidth VINA D0A IF sampling frequencies to 200 MHz DCOA On-chip voltage reference and sample-and-hold circuit VREF 2 V p-p differential analog input SENSE DRVDD AD9628 DNL = 0.25 LSB REF VCM SELECT Serial port control options ORB RBIAS Offset binary, Gray code, or twos complement data format D11B VINB Optional clock duty cycle stabilizer ADC VIN+B D0B Integer 1-to-8 input clock divider Data output multiplex option DCOB Built-in selectable digital test pattern generation DIVIDE DUTY CYCLE MODE Energy-saving power-down modes 1 TO 8 STABILIZER CONTROLS Data clock out with programmable clock and data CLK+ CLK SYNC DCS PDWN DFS OEB alignment NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY SEE FIGURE 7 FOR LVDS PIN NAMES. APPLICATIONS Communications Figure 1. Diversity radio systems Multimode digital receivers PRODUCT HIGHLIGHTS GSM, EDGE, W-CDMA, LTE, 1. The AD9628 operates from a single 1.8 V analog power CDMA2000, WiMAX, TD-SCDMA supply and features a separate digital output driver supply I/Q demodulation systems to accommodate 1.8 V CMOS or LVDS logic families. Smart antenna systems Broadband data applications 2. The patented sample-and-hold circuit maintains excellent Battery-powered instruments performance for input frequencies up to 200 MHz and is Hand-held scope meters designed for low cost, low power, and ease of use. Portable medical imaging 3. A standard serial port interface supports various product Ultrasound features and functions, such as data output formatting, Radar/LIDAR internal clock divider, power-down, DCO/data timing and offset adjustments. 4. The AD9628 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9650/AD9269/ AD9268 16-bit ADC, the AD9258/AD9251/AD9648 14-bit ADCs, the AD9231 12-bit ADC, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com MUX OPTION CMOS/LVDS CMOS/LVDS OUTPUT BUFFER OUTPUT BUFFER 09976-001AD9628 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 27 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 28 Functional Block Diagram .............................................................. 1 Channel/Chip Synchronization ................................................ 30 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 30 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 31 General Description ......................................................................... 3 Timing.......................................................................................... 31 Specifications ..................................................................................... 4 Output Test ...................................................................................... 32 DC Specifications ........................................................................... 4 Output Test Modes ..................................................................... 32 AC Specifications ........................................................................... 5 Serial Port Interface (SPI) .............................................................. 33 Digital Specifications ................................................................... 6 Configuration Using the SPI ..................................................... 33 Switching Specifications ................................................................ 8 Hardware Interface ..................................................................... 34 Timing Specifications .................................................................. 9 Configuration Without the SPI ................................................ 34 Absolute Maximum Ratings .......................................................... 12 SPI Accessible Features .............................................................. 34 Thermal Characteristics ............................................................ 12 Memory Map .................................................................................. 35 ESD Caution ................................................................................ 12 Reading the Memory Map Register Table ............................... 35 Pin Configurations and Function Descriptions ......................... 13 Memory Map Register Table ..................................................... 36 Typical Performance Characteristics ........................................... 19 Memory Map Register Descriptions ........................................ 39 AD9628-125 ................................................................................ 19 Applications Information .............................................................. 41 AD9628-105 ................................................................................ 22 Design Guidelines ...................................................................... 41 Equivalent Circuits ......................................................................... 24 Outline Dimensions ....................................................................... 42 Theory of Operation ...................................................................... 25 Ordering Guide .......................................................................... 42 ADC Architecture ...................................................................... 25 Analog Input Considerations .................................................... 25 REVISION HISTORY 11/15Rev. B to Rev. C Changes to Differential Input Configurations Section ............. 26 Changed AD9516 to AD9516-0/AD9516-1/AD9516-2/ Deleted Figure 48 Renumbered Sequentially ............................ 27 AD9516-3/AD9516-4/AD9516-5, and AD9517 to AD9517-0/ Change to Clock Input Options Section ..................................... 28 AD9517-1/AD9517-2/AD9517-3/AD9517-4 ............ Throughout Changed Built-In Self-Test (BIST) and Output Test Mode Change to Figure 3 ......................................................................... 10 Section to Output Test Section ..................................................... 32 Deleted Built-In Self-Test (BIST) Section ................................... 32 8/15Rev. A to Rev. B Change to Configuration Without the SPI Section ................... 34 Changes to Features Section and Product Highlights Section ... 1 Changes to Channel-Specific Registers Section ......................... 35 Changes to General Description Section ...................................... 3 Changes to Table 18 ....................................................................... 37 Changes to Bit 7OEB Pin Enable Section................................ 40 Changes to Aperture Uncertainty (Jitter, tJ) Parameter, Table 4 ................................................................................................ 8 Added Clock Stability Considerations Section........................... 41 Changes to Table 6 .......................................................................... 12 Updated Outline Dimensions ....................................................... 42 Changes to Table 7 .......................................................................... 12 Changes to RBIAS Pin Description and OEB Pin Description, 11/14Rev. 0 to Rev. A Table 8 .............................................................................................. 13 Changes to Table 10 ....................................................................... 18 Changes to RBIAS Pin Description and OEB Pin Description, Change to Figure 61 Caption ........................................................ 30 Table 9 .............................................................................................. 15 Updated Outline Dimensions ....................................................... 42 Changes to RBIAS Pin Description and OEB Pin Description, Table 10 ............................................................................................ 17 7/11Revision 0: Initial Version Changes to Figure 35 ...................................................................... 24 Rev. C Page 2 of 42