Quad, 12-Bit, 80 MSPS/105 MSPS/ 125 MSPS, Serial LVDS 1.8 V ADC Data Sheet AD9633 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD 1.8 V supply operation 12 Low power: 100 mW per channel at 125 MSPS with scalable D0+A SERIAL VIN+A DIGITAL LVDS D0A PIPELINE power options SERIALIZER VINA ADC D1+A SERIAL LVDS SNR = 71 dB (to Nyquist) 12 D1A VIN+B DIGITAL PIPELINE D0+B SERIAL SFDR = 91 dBc (to Nyquist) VINB SERIALIZER ADC LVDS D0B RBIAS DNL = 0.3 LSB (typical) INL = 0.5 LSB (typical) SERIAL D1+B VREF LVDS D1B Serial LVDS (ANSI-644, default) and low power, reduced SENSE FCO+ 1V signal option (similar to IEEE 1596.3) AD9633 REF FCO SELECT 650 MHz full power analog bandwidth D0+C AGND SERIAL 12 LVDS D0C 2 V p-p input voltage range VIN+C DIGITAL PIPELINE D1+C SERIAL SERIALIZER VINC ADC LVDS Serial port control D1C 12 SERIAL D0+D Full chip and individual channel power-down modes VIN+D LVDS D0D DIGITAL PIPELINE Flexible bit orientation SERIALIZER VIND ADC SERIAL D1+D LVDS D1D Built-in and custom digital test pattern generation SERIAL PORT DCO+ CLOCK Multichip sync and clock divider INTERFACE VCM MANAGEMENT DCO Programmable output clock and data alignment Programmable output resolution Standby mode APPLICATIONS Figure 1. Medical ultrasound High speed imaging Quadrature radio receivers Diversity radio receivers The ADC contains several features designed to maximize Test equipment flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern GENERAL DESCRIPTION generation. The available digital test patterns include built-in The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS deterministic and pseudorandom patterns, along with custom analog-to-digital converter (ADC) with an on-chip sample-and- user-defined test patterns entered via the serial port interface (SPI). hold circuit designed for low cost, low power, small size, and The AD9633 is available in a RoHS-compliant, 48-lead LFCSP. ease of use. The product operates at a conversion rate of up to It is specified over the industrial temperature range of 40C to 125 MSPS and is optimized for outstanding dynamic performance +85C. This product is protected by a U.S. patent. and low power in applications where a small package size is critical. PRODUCT HIGHLIGHTS The ADC requires a single 1.8 V power supply and LVPECL-/ 1. Small Footprint. Four ADCs are contained in a small, space- CMOS-/LVDS-compatible sample rate clock for full performance saving package. operation. No external reference or driver components are 2. Low power of 100 mW/channel at 125 MSPS with scalable required for many applications. power options. 3. Pin compatible to the AD9253 14-bit quad ADC. The ADC automatically multiplies the sample rate clock for the 4. Ease of Use. A data clock output (DCO) operates at appropriate LVDS serial data rate. A data clock output (DCO) for frequencies of up to 375 MHz and supports double data capturing data on the output and a frame clock output (FCO) rate (DDR) operation. for signaling a new output byte are provided. Individual-channel 5. User Flexibility. The SPI control offers a wide range of flexible power-down is supported and typically consumes less than 2 mW features to meet specific system requirements. when all channels are disabled. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. CSB SDIO/OLM SCLK/DTP SYNC CLK+ CLK 10073-001AD9633 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 25 Applications ....................................................................................... 1 Power Dissipation and Power-Down Mode ........................... 27 General Description ......................................................................... 1 Digital Outputs and Timing ..................................................... 28 Functional Block Diagram .............................................................. 1 Output Test Modes ..................................................................... 31 Product Highlights ........................................................................... 1 Serial Port Interface (SPI) .............................................................. 32 Revision History ............................................................................... 2 Configuration Using the SPI ..................................................... 32 Specifications ..................................................................................... 4 Hardware Interface ..................................................................... 33 DC Specifications ......................................................................... 4 Configuration Without the SPI ................................................ 33 AC Specifications .......................................................................... 5 SPI Accessible Features .............................................................. 33 Digital Specifications ................................................................... 6 Memory Map .................................................................................. 34 Switching Specifications .............................................................. 7 Reading the Memory Map Register Table ............................... 34 Timing Specifications .................................................................. 8 Memory Map Register Table ..................................................... 35 Absolute Maximum Ratings .......................................................... 12 Memory Map Register Descriptions ........................................ 38 Thermal Resistance .................................................................... 12 Applications Information .............................................................. 40 ESD Caution ................................................................................ 12 Design Guidelines ...................................................................... 40 Pin Configuration and Function Descriptions ........................... 13 Power and Ground Recommendations ................................... 40 Typical Performance Characteristics ........................................... 15 Clock Stability Considerations ................................................. 40 AD9633-80 .................................................................................. 15 Exposed Pad Thermal Heat Slug Recommendations ............ 40 AD9633-105 ................................................................................ 17 VCM ............................................................................................. 40 AD9633-125 ................................................................................ 19 Reference Decoupling ................................................................ 40 Equivalent Circuits ......................................................................... 22 SPI Port ........................................................................................ 40 Theory of Operation ...................................................................... 23 Crosstalk Performance .............................................................. 41 Analog Input Considerations .................................................... 23 Outline Dimensions ....................................................................... 42 Voltage Reference ....................................................................... 24 Ordering Guide .......................................................................... 42 REVISION HISTORY 9/2019Rev. C to Rev. D 9/2014Rev. 0 to Rev. A Changes to Table 12 ........................................................................ 30 Changes to Table 2 ............................................................................. 4 Updated Outline Dimensions ....................................................... 42 Added Propagation Delay Parameters of 1.5 ns (min) and 3.1 ns (max) Table 4 .................................................................. 6 2/2018Rev. B to Rev. C Changed tSSYNC from 0.24 ns Typ to 1.2 ns Min and Changed Changes to Figure 2 .......................................................................... 7 t from 0.40 ns Typ to 0.2 ns Min Table 5 and Changes to HSYNC Changes to Figure 3 and Figure 4 ................................................... 8 Figure 2 ...............................................................................................7 Changes to Figure 5 .......................................................................... 9 Changes to Figure 3 and Figure 4 .................................................... 8 Change to Table 8 ........................................................................... 13 Changes to Figure 5 ........................................................................... 9 Changes to Power Dissipation and Power-Down Mode Section ... 26 Changes to Pin 9 to Pin 14 and Pin 23 to Pin 28 Descriptions .... 12 Changes to Table 11 ................................................................................... 29 Changes to Figure 47 and Figure 48 ............................................ 21 Updated Outline Dimensions ................................................................. 41 Changes to Clock Input Options Section .................................... 24 Changes to Ordering Guide ..................................................................... 41 Changes to Jitter Considerations Section .................................... 26 Changes to Digital Outputs and Timing Section ....................... 27 10/2015Rev. A to Rev. B Changes to Table 12 ....................................................................... 29 Added Note 4, Table 4 ...................................................................... 6 Changes to Channel-Specific Registers Section ......................... 33 Changes to Digital Outputs and Timing Section ....................... 28 Changes to Output Phase (Register 0x16) Section .................... 37 Changes to Clock Stability Considerations Section ................... 39 Changes to Resolution/Sample Rate Override (Register 0x100) Section .............................................................................................. 38 Added Clock Stability Considerations Section........................... 39 Rev. D Page 2 of 42