12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9634 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 69.7 dBFS at 185 MHz A and 250 MSPS IN SFDR = 87 dBc at 185 MHz A and 250 MSPS IN VIN+ PIPELINE 12 150.6 dBFS/Hz input noise at 185 MHz, 1 dBFS A and D0/D1 IN 12-BIT . ADC 250 MSPS VIN . PARALLEL . DDR LVDS Total power consumption: 360 mW at 250 MSPS VCM AD9634 AND D10/D11 DRIVERS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs REFERENCE DCO Integer 1-to-8 input clock divider (625 MHz maximum input) OR Sample rates of up to 250 MSPS 1-TO-8 SERIAL PORT Internal ADC voltage reference CLOCK DIVIDER Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) SCLK SDIO CSB CLK+ CLK ADC clock duty cycle stabilizer Figure 1. Serial port control Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9634 is a 12-bit, analog-to-digital converter (ADC) with Programming for setup and control is accomplished using a sampling speeds of up to 250 MSPS. The AD9634 is designed to 3-wire, SPI-compatible serial interface. support communications applications where low cost, small size, The AD9634 is available in a 32-lead LFCSP and is specified over wide bandwidth, and versatility are desired. the industrial temperature range of 40C to +85C. This product The ADC core features a multistage, differential pipelined is protected by a U.S. patent. architecture with integrated output error correction logic. The PRODUCT HIGHLIGHTS ADC features wide bandwidth inputs that can support a variety 1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC. of user-selectable input ranges. An integrated voltage reference 2. Fast overrange and threshold detect. eases design considerations. A duty cycle stabilizer (DCS) is 3. Proprietary differential input maintains excellent SNR provided to compensate for variations in the ADC clock duty cycle, performance for input frequencies of up to 350 MHz. allowing the converter to maintain excellent performance. 4. 3-pin, 1.8 V SPI port for register programming and readback. The ADC output data are routed directly to the external 12-bit 5. Pin compatibility with the AD9642, allowing a simple LVDS output port. migration up to 14 bits, and with the AD6672. Flexible power-down options allow significant power savings, when desired. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09996-001AD9634 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Architecture ...................................................................... 19 Applications ....................................................................................... 1 Analog Input Considerations ................................................... 19 Functional Block Diagram .............................................................. 1 Voltage Reference ....................................................................... 21 General Description ......................................................................... 1 Clock Input Considerations ...................................................... 21 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 23 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 23 Specifications ..................................................................................... 3 ADC Overrange (OR) ................................................................ 23 ADC DC Specifications ................................................................. 3 Serial Port Interface (SPI) .............................................................. 24 ADC AC Specifications ................................................................. 4 Configuration Using the SPI ..................................................... 24 Digital Specifications ................................................................... 6 Hardware Interface ..................................................................... 24 Switching Specifications ................................................................ 7 SPI Accessible Features .............................................................. 25 Timing Specifications .................................................................. 8 Memory Map .................................................................................. 26 Absolute Maximum Ratings ............................................................ 9 Reading the Memory Map Register Table ............................... 26 Thermal Characteristics .............................................................. 9 Memory Map Register Table ..................................................... 27 ESD Caution .................................................................................. 9 Applications Information .............................................................. 29 Pin Configuration and Function Descriptions ........................... 10 Design Guidelines ...................................................................... 29 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 30 Equivalent Circuits ......................................................................... 18 Ordering Guide .......................................................................... 30 Theory of Operation ...................................................................... 19 REVISION HISTORY 12/14Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Reading the Memory Map Register Table Section .............................................................................................. 26 Changes to Table 13 ........................................................................ 28 7/14Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Full Power Bandwidth Parameter, Table 2 ................ 5 Deleted Noise Bandwidth Parameter, Table 2............................... 5 7/11Revision 0: Initial Version Rev. B Page 2 of 30