Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9637 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD Low power: 60 mW per channel at 80 MSPS with scalable power options AD9637 12 D+ A VIN+ A SERIAL ADC D A SNR = 71.5 dBFS (to Nyquist) VIN A LVDS SFDR = 92 dBc (to Nyquist) 12 D+ B VIN+ B SERIAL DNL = 0.4 LSB (typical), INL = 0.5 LSB (typical) ADC D B LVDS VIN B Serial LVDS (ANSI-644, default) 12 D+ C VIN+ C Low power, reduced signal option (similar to IEEE 1596.3) SERIAL ADC D C LVDS VIN C Data and frame clock outputs 12 D+ D 650 MHz full power analog bandwidth VIN+ D SERIAL ADC D D LVDS VIN D 2 V p-p differential input voltage range 12 D+ E 1.8 V supply operation VIN+ E SERIAL ADC D E LVDS VIN E Serial port control Full chip and individual channel power-down modes 12 D+ F VIN+ F SERIAL ADC D F Flexible bit orientation LVDS VIN F Built-in and custom digital test pattern generation 12 D+ G VIN+ G SERIAL ADC D G Programmable clock and data alignment LVDS VIN G Programmable output resolution 12 D+ H VIN+ H SERIAL Standby mode ADC D H LVDS VIN H APPLICATIONS VREF SENSE FCO+ 1.0V Medical imaging and nondestructive ultrasound DATA FCO VCM REF SERIAL PORT RATE Portable ultrasound and digital beam-forming systems DCO+ MULTIPLIER SELECT INTERFACE DCO Quadrature radio receivers SYNC Diversity radio receivers RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK Optical networking DFS DTP Test equipment Figure 1. GENERAL DESCRIPTION clock and data alignment and programmable digital test pattern The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital generation. The available digital test patterns include built-in converter (ADC) with an on-chip sample-and-hold circuit deterministic and pseudorandom patterns, along with custom user- designed for low cost, low power, small size, and ease of use. defined test patterns entered via the serial port interface (SPI). The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is power in applications where a small package size is critical. specified over the industrial temperature range of 40C to +85C. This product is protected by a U.S. patent. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance PRODUCT HIGHLIGHTS operation. No external reference or driver components are 1. Small Footprint. Eight ADCs are contained in a small, required for many applications. space-saving package. The ADC automatically multiplies the sample rate clock for the 2. Low Power of 60 mW/Channel at 80 MSPS with Scalable appropriate LVDS serial data rate. A data clock output (DCO) for Power Options. capturing data on the output and a frame clock output (FCO) for 3. Ease of Use. A data clock output (DCO) is provided that signaling a new output byte are provided. Individual channel operates at frequencies of up to 480 MHz and supports power-down is supported and typically consumes less than 2 mW double data rate (DDR) operation. when all channels are disabled. 4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. The ADC contains several features designed to maximize 5. Pin Compatible with the AD9257 (14-Bit Octal ADC). flexibility and minimize system cost, such as programmable Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 10215-001AD9637 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Power-Down Mode ........................... 22 Applications ....................................................................................... 1 Digital Outputs and Timing ..................................................... 23 General Description ......................................................................... 1 Built-In Output Test Modes .......................................................... 27 Functional Block Diagram .............................................................. 1 Output Test Modes ..................................................................... 27 Product Highlights ........................................................................... 1 Serial Port Interface (SPI) .............................................................. 28 Revision History ............................................................................... 2 Configuration Using the SPI ..................................................... 28 Specif icat ions ..................................................................................... 3 Hardware Interface ..................................................................... 29 DC Specifications ......................................................................... 3 Configuration Without the SPI ................................................ 29 AC Specifications .......................................................................... 4 SPI Accessible Features .............................................................. 29 Digital Specifications ................................................................... 5 Memory Map .................................................................................. 30 Switching Specifications .............................................................. 6 Reading the Memory Map Register Table ............................... 30 Timing Specifications .................................................................. 6 Memory Map Register Table ..................................................... 31 Absolute Maximum Ratings ............................................................ 8 Memory Map Register Descriptions ........................................ 34 Thermal Characteristics .............................................................. 8 Applications Information .............................................................. 36 ESD Caution .................................................................................. 8 Design Guidelines ...................................................................... 36 Pin Configuration and Function Descriptions ............................. 9 Power and Ground Recommendations ................................... 36 Typical Performance Characteristics ........................................... 11 Clock Stability Considerations ................................................. 36 AD9637-80 .................................................................................. 11 Exposed Pad Thermal Heat Slug Recommendations ............ 36 AD9637-40 .................................................................................. 14 VCM ............................................................................................. 36 Equivalent Circuits ......................................................................... 17 Reference Decoupling ................................................................ 36 Theory of Operation ...................................................................... 18 SPI Port ........................................................................................ 36 Analog Input Considerations .................................................... 18 Outline Dimensions ....................................................................... 37 Voltage Reference ....................................................................... 19 Ordering Guide .......................................................................... 37 Clock Input Considerations ...................................................... 20 REVISION HISTORY 4/13Rev. 0 to Rev. A Added Common-Mode Range ....................................................... 3 Changes to AC Specifications Section ........................................... 4 Added Propagation Delay of 1.5 ns Min and 3.1 ns Max Table 4 .. 6 Added CLK Divider = 8 to Figure 7, Figure 9, Figure 10, and Figure 11 Captions .......................................................................... 11 Added CLK Divider = 8 to Figure 22, Figure 24, and Figure 25 Captions ........................................................................................... 14 Changes to Figure 36 and Figure 37 ............................................. 17 Changes to Figure 44 ...................................................................... 18 Changes to Figure 56 ...................................................................... 22 Changes to Digital Outputs and Timing Section ....................... 23 Changes to Channel Specific Registers Section .......................... 30 Changes to Register 0x21, Bit 3 Table 17 .................................... 33 Changes to Bits 6:4 Input Clock Phase Adjust Section......... 35 Added Clock Stability Considerations Section ........................... 36 Updated Outline Dimensions ....................................................... 37 10/11Revision 0: Initial Version Rev. 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