16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9652 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD3 AVDD SDIO SCLK CSB DRVDD High dynamic range SNR = 75.0 dBFS at 70 MHz (A = 1 dBFS) IN SPI SFDR = 87 dBc at 70 MHz (A = 1 dBFS) IN AD9652 Noise spectral density (NSD) = 156.7 dBFS/Hz input noise OR+, OR at 1 dBFS at 70 MHz PROGRAMMING DATA NSD = 157.6 dBFS/Hz for small signal at 7 dBFS at 70 MHz VIN+A DDR DATA D15 (MSB) 16 ADC INTERLEAVER TO 90 dB channel isolation/crosstalk VINA LVDS OUTPUT D0 (LSB)* DRIVER On-chip dithering (improves small signal linearity) Excellent IF sampling performance VREF CLK+ DIVIDE 1 = 1 dBFS) SNR = 73.7 dBFS at 170 MHz (AIN TO 8 SENSE CLK SFDR = 85 dBc at 170 MHz (A = 1 dBFS) IN Full power bandwidth of 465 MHz DCO+ REF DUTY CYCLE DCO SELECT STABILIZER GENERATION VCM On-chip 3.3 V buffer DCO Programmable input span of 2 V p-p to 2.5 V p-p (default) RBIAS Differential clock input receiver with 1, 2, 4, and 8 integer VINB ADC inputs (clock divider input accepts up to 1.24 GHz) MULTICHIP VIN+B SYNC Internal ADC clock duty cycle stabilizer SYNC input allows multichip synchronization AGND SYNC PDWN Total power consumption: 2.16 W *THESE PINS ARE FOR CHANNEL A AND CHANNEL B. 3.3 V and 1.8 V supply voltages Figure 1. DDR LVDS (ANSI-644 levels) outputs Serial port control Energy saving power-down modes APPLICATIONS Military radar and communications Multimode digital receivers (3G or 4G) Test and instrumentation Smart antenna systems The 16-bit output data (with an overrange bit) from each ADC GENERAL DESCRIPTION is interleaved onto a single LVDS output port along with a The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) double data rate (DDR) clock. Programming for setup and control with sampling speeds of up to 310 MSPS. It is designed to are accomplished using a 3-wire SPI-compatible serial interface. support demanding, high speed signal processing applications The AD9652 is available in a 144-ball CSP BGA and is that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise specified over the industrial temperature range of 40C to floor of 157.6 dBFS and large signal spurious-free dynamic +85C. This product is protected by pending U.S. patents. range (SFDR) performance (exceeding 85 dBFS, typical) allows PRODUCT HIGHLIGHTS low level signals to be resolved in the presence of large signals. 1. Integrated dual, 16-bit, 310 MSPS ADCs. The dual ADC cores feature a multistage, pipelined architecture 2. On-chip buffer simplifies ADC driver interface. with integrated output error correction logic. A high performance 3. Operation from 3.3 V and 1.8 V supplies and a separate on-chip buffer and internal voltage reference simplify the inter- digital output driver supply accommodating LVDS outputs. face to external driving circuitry while preserving the exceptional 4. Proprietary differential input maintains excellent signal-to- performance of the ADC. noise ratio (SNR) performance for input frequencies of up The AD9652 can support input clock frequencies of up to to 485 MHz. 1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate 5. SYNC input allows synchronization of multiple devices. the ADC sample clock. A duty cycle stabilizer is provided to 6. Three-wire, 3.3 V or 1.8 V SPI port for register programming compensate for variations in the ADC clock duty cycle. and readback. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12169-001AD9652 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 23 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 25 General Description ......................................................................... 1 Internal Background Calibration ............................................. 25 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 26 Revision History ............................................................................... 2 ADC Overrange .......................................................................... 26 Specifications ..................................................................................... 3 Fast Threshold Detection (FDA/FDB) ........................................ 28 ADC DC Specifications ............................................................... 3 Serial Port Interface ........................................................................ 29 ADC AC Specifications ............................................................... 4 Configuration Using the SPI ..................................................... 29 Digital Specifications ................................................................... 5 Hardware Interface ..................................................................... 29 Switching Specifications .............................................................. 7 Configuration Without the SPI ................................................ 29 Timing Specifications .................................................................. 7 SPI Accessible Features .............................................................. 30 Absolute Maximum Ratings ............................................................ 9 Memory Map .................................................................................. 31 Thermal Characteristics .............................................................. 9 Reading the Memory Map Register Table ............................... 31 ESD Caution .................................................................................. 9 Memory Map Register Table ..................................................... 32 Applications Information .............................................................. 35 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 13 Design Guidelines ...................................................................... 35 Equivalent Circuits ......................................................................... 19 Outline Dimensions ....................................................................... 36 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 36 ADC Architecture ...................................................................... 20 Analog Input Considerations .................................................... 20 REVISION HISTORY 1/2018Rev. B to Rev. C 5/2014Rev. 0 to Rev. A Changes to Transfer Register Map Section ................................. 31 Changes to Supply Current, Clock Divider = 1 Parameter and Changes to Table 17 ........................................................................ 34 Power Consumption, Clock Divider = 1 Parameter, Table 1 ....... 3 Changes to Ordering Guide .......................................................... 36 4/2014Revision 0: Initial Version 1/2017Rev. A to Rev. B Changes to DCO to Data Skew (tSKEW) Parameter, Table 4 ............. 7 Changes to Clock Input Options Section .................................... 24 Rev. C Page 2 of 36