Dual, 16-Bit, 125 MSPS Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9655 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD 1.8 V supply operation Low power: approximately 150 mW/channel at 125 MSPS, AD9655 D0A+ 2 V p-p input range (typical) 16 D0A VINA+ 16-BIT D1A+ SNR/SFDR at 69.5 MHz PIPELINE D1A VINA ADC 77.5 dBFS/88 dBc, 2.0 V p-p input range (typical) D0B+ 16 D0B VCM 79.3 dBFS/84 dBc, 2.8 V p-p input range (typical) 16 D1B+ VINB+ 16-BIT Linearity D1B PIPELINE DCO+ VINB ADC DNL = 0.7 LSB INL = 4.0 LSB (typical, 2.0 V p-p input span) DCO 16 DNL = 0.7 LSB INL = 3.4 LSB (typical, 2.8 V p-p input span) FCO+ REFERENCE FCO Serial LVDS, two data lanes per ADC channel SERIAL PORT 1 TO 8 500 MHz full power analog bandwidth INTERFACE CLOCK DIVIDER Serial port control SCLK/ SDIO/ CSB CLK+ CLK Full chip and individual channel power-down modes DFS PDWN Flexible bit orientation Figure 1. Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Standby mode APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Individual channel power-down is supported. The AD9655 Battery-powered instruments typically consumes less than 2 mW in serial port interface (SPI) Handheld scope meters power-down mode. The available digital test pat-terns include Portable medical imaging and ultrasound built-in deterministic and pseudorandom patterns, along with Radar/LIDAR custom user-defined test patterns entered via the SPI. GENERAL DESCRIPTION The AD9655 is available in an RoHS-compliant, 32-lead LFCSP. The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital It is specified over the industrial temperature range of 40C to converter (ADC) with an on-chip sample-and-hold circuit +85C. This device is protected by a U.S. patent. designed for low cost, low power, small size, and ease of use. PRODUCT HIGHLIGHTS The product operates at a conversion rate of up to 125 MSPS 1. Small Footprint. and is optimized for outstanding dynamic performance and low Two ADCs are contained in a small, space-saving package. power in applications where a small package size is critical. 2. Pin Compatible. The ADC requires a single 1.8 V power supply and an LVPECL-/ The AD9655 is pin compatible to the AD9645 14-bit and CMOS-/LVDS-compatible sample rate clock for full performance AD9635 12-bit dual ADCs. operation. External reference or driver components are not 3. Ease of Use. required for many applications. A DCO operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. The ADC automatically multiplies the sample rate clock for the 4. User Flexibility. appropriate LVDS serial data rate. A data clock output (DCO) The SPI control offers a wide range of flexible features to for capturing data on the output and a frame clock output (FCO) meet specific system requirements. for signaling a new output byte are provided. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com PLL, SERIALIZER AND DDR LVDS DRIVERS 12737-001AD9655 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 22 Applications ....................................................................................... 1 Power Dissipation and Power-Down Mode ........................... 23 General Description ......................................................................... 1 Digital Outputs and Timing ..................................................... 24 Functional Block Diagram .............................................................. 1 Output Test Modes ..................................................................... 27 Product Highlights ........................................................................... 1 Serial Port Interface (SPI) .............................................................. 28 Revision History ............................................................................... 2 Configuration Using the SPI ..................................................... 28 Specifications ..................................................................................... 3 Hardware Interface ..................................................................... 29 DC Specifications ......................................................................... 3 Configuration Without the SPI ................................................ 29 AC Specifications .......................................................................... 5 SPI Accessible Features .............................................................. 29 Digital Specifications ................................................................... 7 Memory Map .................................................................................. 30 Switching Specifications .............................................................. 8 Reading the Memory Map Register Table ............................... 30 Timing Specifications .................................................................. 8 Memory Map Register Table ..................................................... 31 Absolute Maximum Ratings .......................................................... 10 Memory Map Register Descriptions ........................................ 34 Thermal Resistance .................................................................... 10 Applications Information .............................................................. 36 ESD Caution ................................................................................ 10 Design Guidelines ...................................................................... 36 Pin Configuration and Function Descriptions ........................... 11 Power and Ground Guidelines ................................................. 36 Typical Performance Characteristics ........................................... 12 Clock Stability Considerations ................................................. 36 VREF = 1.0 V ................................................................................. 12 Exposed Pad Thermal Heat Slug Recommendations ............ 36 VREF = 1.4 V ................................................................................. 15 VCM ............................................................................................. 36 Equivalent Circuits ......................................................................... 18 Reference Bypassing ................................................................... 36 Theory of Operation ...................................................................... 19 SPI Port ........................................................................................ 36 Analog Input Considerations .................................................... 19 Outline Dimensions ....................................................................... 37 Voltage Reference ....................................................................... 20 Ordering Guide .......................................................................... 37 REVISION HISTORY 1/15Revision 0: Initial Version Rev. 0 Page 2 of 37