Quad, 16-Bit, 125 MSPS, JESD204B 1.8 V Analog-to-Digital Converter Data Sheet AD9656 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DVDD DRVDD SNR = 79.9 dBFS at 16 MHz (V = 1.4 V) REF SNR = 78.1 dBFS at 64 MHz (V = 1.4 V) REF 16 VINA+ SERDOUT0+ PIPELINE JESD204B SFDR = 86 dBc to Nyquist (V = 1.4 V) REF SERDOUT0 VINA ADC INTERFACE JESD204B Subclass 1 coded serial digital outputs SERDOUT1+ 16 VINB+ SERDOUT1 PIPELINE CML TX Flexible analog input range: 2.0 V p-p to 2.8 V p-p VINB ADC OUTPUTS SERDOUT2+ RBIAS 1.8 V supply operation SERDOUT2 VREF Low power: 197 mW per channel at 125 MSPS (two lanes) SERDOUT3+ HIGH SENSE 1V SPEED SERDOUT3 DNL = 0.6 LSB (V = 1.4 V) TO REF REF SERIALIZERS 1.4V SELECT SYNCINB+ INL = 4.5 LSB (V = 1.4 V) REF SYNCINB AGND 650 MHz analog input bandwidth, full power 16 VINC+ PIPELINE VINC ADC Serial port control Full chip and individual channel power-down modes CONTROL 16 VIND+ REGISTERS PIPELINE Built-in and custom digital test pattern generation VIND ADC Multichip sync and clock divider SERIAL PORT CLOCK AD9656 Standby mode INTERFACE VCM MANAGEMENT APPLICATIONS Medical ultrasound and MRI High speed imaging Figure 1. Quadrature radio receivers Diversity radio receivers The AD9656 is available in an RoHS compliant, nonmagnetic, Portable test equipment 56-lead LFCSP. It is specified over the 40C to +85C industrial temperature range. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital 1. It has a small footprint. Four ADCs are contained in a small, converter (ADC) with an on-chip sample and hold circuit 8 mm 8 mm package. designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and 2. An on-chip phase-locked loop (PLL) allows users to provide is optimized for outstanding dynamic performance and low a single ADC sampling clock the PLL multiplies the ADC power in applications where a small package size is critical. sampling clock to produce the corresponding JESD204B data rate clock. The ADC requires a single 1.8 V power supply and LVPECL-/ 3. The configurable JESD204B output block supports up to CMOS-/LVDS-compatible sample rate clock for full performance 8.0 Gbps per lane. operation. An external reference or driver components are not 4. JESD204B output block supports one, two, and four lane required for many applications. configurations. Individual channel power-down is supported and typically 5. Low power of 198 mW per channel at 125 MSPS, two lanes. consumes less than 14 mW when all channels are disabled. The 6. The SPI control offers a wide range of flexible features to ADC contains several features designed to maximize flexibility meet specific system requirements. and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudo- random patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. 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CSB SDIO SCLK SVDD SYNC SYSREF+/ SYSREF CLK+/ CLK DVSS 11868-001AD9656 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 21 Applications ....................................................................................... 1 Voltage Reference ....................................................................... 23 General Description ......................................................................... 1 Clock Input Considerations ...................................................... 24 Functional Block Diagram .............................................................. 1 Power Dissipation and Power-Down Mode ........................... 26 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 26 Revision History ............................................................................... 2 Serial Port Interface (SPI) .............................................................. 35 Specif icat ions ..................................................................................... 3 Configuration Using the SPI ..................................................... 35 DC Specifications, V = 1.4 V .................................................. 3 Hardware Interface ..................................................................... 35 REF DC Specifications, VREF = 1.0 V .................................................. 4 SPI Accessible Features .............................................................. 35 AC Specifications, VREF = 1.4 V .................................................. 5 Memory Map .................................................................................. 37 AC Specifications, VREF = 1.0 V .................................................. 6 Reading the Memory Map Register Table ............................... 37 Digital Specifications ................................................................... 7 Memory Map Register Table ..................................................... 38 Switching Specifications .............................................................. 8 Memory Map Register Descriptions ........................................ 42 Timing Specifications .................................................................. 9 Applications Information .............................................................. 44 Absolute Maximum Ratings .......................................................... 11 Design Guidelines ...................................................................... 44 Thermal Resistance .................................................................... 11 Power and Ground Recommendations ................................... 44 ESD Caution ................................................................................ 11 Clock Stability Considerations ................................................. 44 Pin Configuration and Function Descriptions ........................... 12 Exposed Pad Thermal Heat Slug Recommendations ............ 44 Typical Performance Characteristics ........................................... 14 Reference Decoupling ................................................................ 44 VREF = 1.4 V ................................................................................. 14 SPI Port ........................................................................................ 44 V = 1.0 V ................................................................................. 17 Outline Dimensions ....................................................................... 45 REF Equivalent Circuits ......................................................................... 20 Ordering Guide .......................................................................... 45 Theory of Operation ...................................................................... 21 REVISION HISTORY 3/2017Rev. 0 to Rev. A Changes to Input Clock Divider Section ..................................... 25 Changed DSYNC to SYNCINB, to SYSREF, DSYNC to Changes to Power Dissipation and Power-Down Mode Section ... 26 SYNCINB, and DSYSREF to SYSREF .................... Throughout Change to JESD204B Transmit Top Level Description Section ..... 26 Changes to Applications Section, General Description Section, and Added JESD204B Configurations Section Title, Initial JESD204B Product Highlights Section ................................................................ 1 Link Startup Section, and Figure 65 .................................................. 27 Changes to Table 1 ............................................................................ 3 Added Resynchronization Section and Figure 66 ......................... 28 Changes to Table 2 ............................................................................ 4 Changes to CGS Phase Section and ILAS Phase Section ............ 29 Changes to AC Specifications, V = 1.4 V Section and Table 3 .... 5 Added Figure 67 ....................................................................................... 29 REF Change to AC Specifications, V = 1.0 V Section ..................... 6 Change to Set Additional Digital Output Configuration REF Changes to Worst Other Spur or Harmonic (Excluding Second Options Section ........................................................................................ 31 or Third) Parameter, Table 4, Digital Specifications Section, Changes to Figure 68 and Figure 68 ..................................................... 32 and Table 5 ......................................................................................... 7 Changes to Digital Outputs and Timing Section and Figure 71 ..... 33 Changes to Table 6 ............................................................................ 8 Changes to Hardware Interface Section .............................................. 35 Changes to Table 6 Endnotes .......................................................... 9 Changes to Table 19 ................................................................................. 39 Changes to Figure 2 Caption ........................................................... 10 Change to Transfer (Register 0xFF) Section ................................... 42 Change to Table 8 ........................................................................... 11 Changes to Resolution/Sample Rate Override (Register 0x100) .... 43 Changes to Table 10 ........................................................................ 12 Changes to Power and Ground Recommendations Section and Clock Stability Considerations Section ............................................ 44 Changes to Figure 39, Figure 41, Figure 41 Caption, and Figure 44 ................................................................................... 20 Added Figure 42, Renumbered Sequentially .............................. 20 12/2013Revision 0: Initial Version Rev. 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