a Ultrafast Comparators AD96685/AD96687 FEATURES AD96685 FUNCTIONAL BLOCK DIAGRAM Fast: 2.5 ns Propagation Delay NONINVERTING Low Power: 118 mW per Comparator Q OUTPUT INPUT Packages: DIP, SOIC, PLCC INVERTING Q OUTPUT INPUT Power Supplies: +5 V, 5.2 V R R L L Logic Compatibility: ECL 50 ps Delay Dispersion LATCH V T ENABLE APPLICATIONS High Speed Triggers High Speed Line Receivers AD96687 FUNCTIONAL BLOCK DIAGRAM Threshold Detectors NONINVERTING NONINVERTING Window Comparators INPUT Q OUTPUT Q OUTPUT INPUT Peak Detectors Q OUTPUT Q OUTPUT INVERTING INVERTING R R R R INPUT L L L L INPUT LE LE LE LE V T LATCH LATCH ENABLE ENABLE THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULL-DOWN RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50 -200 CONNECTED TO 2.0V, OR 200 -2000 GENERAL DESCRIPTION The AD96685 and AD96687 are ultrafast voltage comparators. The AD96685 is a single comparator with 2.5 ns propagation delay the AD96687 is an equally fast dual comparator. Both devices feature 50 ps propagation delay dispersion which is a particularly important characteristic of high-speed comparators. It is a measure of the difference in propagation delay under differing overdrive conditions. A fast, high precision differential input stage permits consistent propagation delay with a wide variety of signals in the common- mode range from 2.5 V to +5 V. Outputs are complementary digital signals fully compatible with ECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 to 2 V. A level sensitive latch input which permits tracking, track-hold, or sample-hold modes of operation is included. The AD96685 is available in industrial 25C to +85C range in 16-pin SOIC. The AD96687 is available in industrial range 25C to +85C, in 16-pin DIP, SOIC, and 20-lead PLCC. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 2001AD96685/AD96687SPECIFICATIONS ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = 5.0 V Negative Supply Voltage = 5.2 V, unless otherwise noted.) Industrial Temperature Range 25 C to +85 C Test AD96685BR AD96687BQ/BP/BR Parameter Temp Level Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Offset Voltage 25CI 12 1 2 mV Full VI 3 3 mV Input Offset Drift Full V 20 20 V/C Input Bias Current 25CI 710 7 10 A Full VI 13 13 A Input Offset Current 25C I 0.1 1.0 0.1 1.0 A Full VI 1.2 1.2 A Input Resistance 25C V 200 200 k Input Capacitance 25CV 2 2 pF 2 Input Voltage Ranges Full VI 2.5 +5.0 2.5 +5.0 V Common-Mode Rejection Ratio Full VI 80 90 80 90 dB ENABLE INPUT Logic 1 Voltage Full VI 1.1 1.1 V Logic 0 Voltage Full VI 1.5 1.5 V Logic 1 Current Full VI 40 40 A Logic 0 Current Full VI 5 5 A 3 DIGITAL OUTPUTS Logic 1 Voltage Full VI 1.1 1.1 V Logic 0 Voltage Full VI 1.5 1.5 V SWITCHING PERFORMANCES 4 Propagation Delays Input to Output HIGH 25C IV 2.5 3.5 2.5 3.5 ns Input to Output LOW 25C IV 2.5 3.5 2.5 3.5 ns Latch Enable to Output HIGH 25C IV 2.5 3.5 2.5 3.5 ns Latch Enable to Output LOW 25C IV 2.5 3.5 2.5 3.5 ns 5 Dispersions 25C V 50 50 ps Latch Enable Minimum Pulsewidth 25C IV 2.0 3.0 2.0 3.0 ns Minimum Setup Time 25C IV 0.5 1.0 0.5 1.0 ns Minimum Hold Time 25C IV 0.5 1.0 0.5 1.0 ns 6 POWER SUPPLY Positive Supply Current (+5.0 V) Full VI 8 9 15 18 mA Negative Supply Current (5.2 V) Full VI 15 18 31 36 mA 7 Power Supply Rejection Ratio Full VI 60 70 60 70 dB NOTES 1 R = 100 . S 2 Input Voltage Range can be extended to 3.3 V if V = 6.0 V. S 3 Outputs terminated through 50 to 2.0 V. 4 Propagation delays measured with 100 mV pulse (10 mV overdrive) to 50% transition point of the output. 5 Change in propagation delay from 100 mV to 1 V input overdrive. 6 Supply voltages should remain stable within 5% for normal operation. 7 Measured at 5% of +V and V . S S Specifications subject to change without notice. COMPARE LATCH 50% ENABLE t Minimum Setup Time S t S LATCH t t Minimum Hold Time H H t (E) PW V DD DIFFERENTIAL t Input to Output Delay PD INPUT V IN V VOLTAGE OS t (E) LATCH ENABLE to Output Delay PD t (E) PD t PD t (E) Minimum LATCH ENABLE Pulsewidth Q PW 50% V Input Offset Voltage OS V Overdrive Voltage OD 50% Q Figure 1. System Timing Diagram 2 REV. D