JESD204B Octal Ultrasound AFE with Digital Demodulator Data Sheet AD9671 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and digital demodulator/ The AD9671 is designed for low cost, low power, small size, and decimator ease of use for medical ultrasound applications. It contains eight Low power: 150 mW per channel, time gain compensation channels of a VGA with an LNA, a CW harmonic rejection I/Q (TGC) mode, 40 MSPS demodulator with programmable phase rotation, an AAF, an 62.5 mW per channel, continuous wave (CW) mode ADC, and a digital demodulator and decimator for data <30 mW in power-down mode processing and bandwidth reduction. 10 mm 10 mm, 144-ball CSP BGA Each channel features a maximum gain of up to 52 dB, a fully TGC channel input referred noise: 0.82 nV/ Hz, differential signal path, and an active input preamplifier termination. maximum gain The channel is optimized for high dynamic performance and Flexible power-down modes low power in applications where a small package size is critical. Fast recovery from low power standby mode: <2 s Low noise preamplifier (LNA) The LNA has a single-ended to differential gain that is selectable Input referred noise: 0.78 nV/Hz, gain = 21.6 dB through the serial port interface (SPI). Assuming a 15 MHz noise Programmable gain: 15.6 dB/17.9 dB/21.6 dB bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR 0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p is 94 dB. In CW Doppler mode, each LNA output drives an I/Q Flexible active input impedance matching demodulator that has independently programmable phase Variable gain amplifier (VGA) rotation with 16 phase settings. Attenuator range: 45 dB, linear-in-dB gain control Power-down of individual channels is supported to increase Postamplifier (PGA) gain: 21 dB/24 dB/27 dB/30 dB battery life for portable applications. Standby mode allows quick Antialiasing filter (AAF) power-up for power cycling. In CW Doppler operation, the Programmable, second-order low-pass filter (LPF) from VGA, AAF, and ADC are powered down. The ADC contains 8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass several features designed to maximize flexibility and minimize filter (HPF) system cost, such as a programmable clock, data alignment, and Analog-to-digital converter (ADC) programmable digital test pattern generation. The digital test Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS patterns include built-in fixed patterns, built-in pseudorandom JESD204B Subclass 0 coded serial digital outputs patterns, and custom user defined test patterns entered via the SPI. CW Doppler (CWD) mode harmonic rejection I/Q demodulator Individual programmable phase rotation Dynamic range per channel: 160 dBFS/Hz Close-in SNR: 156 dBc/Hz, 1 kHz oset, 3 dBFS input Digital demodulator/decimator I/Q demodulator with programmable oscillator APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9671 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CW Doppler Operation ............................................................. 39 Applications ....................................................................................... 1 Digital Demodulator/Decimator .................................................. 40 General Description ......................................................................... 1 Vector Profile .............................................................................. 40 Revision History ............................................................................... 2 RF Decimator .............................................................................. 41 Functional Block Diagram .............................................................. 3 Baseband Demodulator and Decimator.................................. 42 Specif icat ions ..................................................................................... 4 Digital Test Waveforms .............................................................. 43 AC Specifications .......................................................................... 4 Digital Block Power Saving Scheme ........................................ 43 Digital Specifications ................................................................... 8 Serial Port Interface (SPI) .............................................................. 44 Switching Specifications .............................................................. 9 Hardware Interface ..................................................................... 44 Absolute Maximum Ratings .......................................................... 12 Memory Map .................................................................................. 46 Thermal Impedance ................................................................... 12 Reading the Memory Map Table .............................................. 46 ESD Caution ................................................................................ 12 Reserved Locations .................................................................... 46 Pin Configuration and Function Descriptions ........................... 13 Default Values ............................................................................. 46 Typical Performance Characteristics ........................................... 16 Logic Levels ................................................................................. 46 TGC Mode ................................................................................... 16 Recommended Start-Up Sequence .......................................... 46 CW Doppler Mode ..................................................................... 20 Memory Map Register Descriptions ........................................ 59 Theory of Operation ...................................................................... 21 Outline Dimensions ....................................................................... 60 TGC Operation ........................................................................... 21 Ordering Guide .......................................................................... 60 Digital Outputs and Timing ...................................................... 29 Analog Test Tone Generation ................................................... 38 REVISION HISTORY 1/16Revision A: Initial Version Rev. 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