Octal Ultrasound Analog Front End Data Sheet AD9674 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and digital RF decimator The AD9674 is designed for low cost, low power, small size, and Low power: 150 mW per channel, TGC mode, 40 MSPS ease of use for medical ultrasound. It contains eight channels of a 62.5 mW per channel, CW mode <30 mW in power-down VGA with an LNA, a CW harmonic rejection I/Q demodulator Time gain compensation (TGC) channel input referred noise: with programmable phase rotation, an AAF, an ADC, a digital 0.82 nV/Hz, maximum gain HPF, and RF decimation by 2. Flexible power-down modes Each channel features a maximum gain of up to 52 dB, a fully Fast recovery from low power standby mode: <2 s differential signal path, and an active input preamplifier termination. Low noise preamplifier (LNA) The channel is optimized for high dynamic performance and Input referred noise voltage: 0.78 nV/Hz, gain = 21.6 dB low power in applications where a small package size is critical. Programmable gain: 15.6 dB/17.9 dB/21.6 dB The LNA has a single-ended to differential gain that is selectable 0.1 dB compression: 1.00 V p-p/ through the serial port interface (SPI). Assuming a 15 MHz noise 0.75 V p-p/0.45 V p-p bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is Flexible active input impedance matching 94 dB. In CW Doppler mode, each LNA output drives an I/Q Variable gain amplifier (VGA) demodulator that has independently programmable phase Attenuator range: 45 dB, linear in dB gain control rotation with 16 phase settings. Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB Antialiasing filter (AAF) Power-down of individual channels is supported to increase battery Programmable second-order low-pass filter (LPF) from 8 MHz life for portable applications. Standby mode allows quick power-up to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter (HPF) for power cycling. In CW Doppler operation, the VGA, AAF, and Analog-to-digital converter (ADC) ADC are powered down. The ADC contains several features Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS designed to maximize flexibility and minimize system cost, such as Configurable serial low voltage differential signaling (LVDS) a programmable clock, data alignment, and programmable digital Continuous wave (CW) Doppler mode harmonic rejection I/Q test pattern generation. The digital test patterns include built in demodulator fixed patterns, built in pseudorandom patterns, and custom Individual programmable phase rotation user defined test patterns entered via the SPI. Dynamic range per channel: >160 dBFS/Hz Close in SNR: 156 dBc/Hz, 1 kHz offset, 3 dBFS input Radio frequency (RF) digital HPF and decimation by 2 10 mm 10 mm, 144-ball CSP BGA APPLICATIONS Medical imaging/ultrasound Nondestructive Testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD9674 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Test Signal Generation ................................................. 31 Applications ....................................................................................... 1 CW Doppler Operation ............................................................. 32 General Description ......................................................................... 1 Digital RF Decimator ..................................................................... 33 Revision History ............................................................................... 2 Vector Profile .............................................................................. 33 Functional Block Diagram .............................................................. 3 RF Decimator .............................................................................. 34 Specifications ..................................................................................... 4 Digital Test Waveforms .............................................................. 34 AC Specifications .......................................................................... 4 Digital block Power Saving scheme ......................................... 35 Digital Specifications ................................................................... 7 Serial Port Interface (SPI) ................................................................ 36 Switching Specifications .............................................................. 8 Hardware Interface ..................................................................... 36 ADC Timing Diagram ................................................................. 9 Memory Map .................................................................................. 38 CW Doppler Timing Diagram ................................................... 9 Reading the Memory Map Table .............................................. 38 Absolute Maximum Ratings .......................................................... 11 Reserved Locations .................................................................... 38 Thermal Impedance ................................................................... 11 Default Values ............................................................................. 38 ESD Caution ................................................................................ 11 Logic Levels ................................................................................. 38 Pin Configuration and Function Descriptions ........................... 12 Recommended Start-Up Sequence .......................................... 38 Typical Performance Characteristics ........................................... 15 Memory Map Register Descriptions ........................................ 46 TGC Mode ................................................................................... 15 Outline Dimensions ....................................................................... 47 CW Doppler Mode ..................................................................... 19 Ordering Guide .......................................................................... 47 Theory of Operation ...................................................................... 20 TGC Operation ........................................................................... 20 REVISION HISTORY 1/16Revision A: Initial Version Rev. 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