Octal Ultrasound AFE with JESD204B Data Sheet AD9675 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and digital RF decimator The AD9675 is designed for low cost, low power, small size, and Low power ease of use for medical ultrasound. It contains eight channels of 150 mW per channel, TGC mode, 40 MSPS a variable gain amplifier (VGA) with a low noise preamplifier 62.5 mW per channel, CW mode (LNA), a continuous wave (CW) harmonic rejection I/Q 10 mm 10 mm, 144-ball CSP BGA demodulator with programmable phase rotation, an antialiasing TGC channel input referred noise: 0.82 nV/Hz, filter (AAF), an analog-to-digital converter (ADC), and a digital maximum gain high-pass filter and RF decimation by 2 for data processing and Flexible power-down modes bandwidth reduction. Fast recovery from low power standby mode: 2 s Each channel features a maximum gain of up to 52 dB, a fully Low noise preamplifier (LNA) differential signal path, and an active input preamplifier termina- Input referred noise: 0.78 nV/Hz, gain = 21.6 dB tion. The channel is optimized for high dynamic performance Programmable gain: 15.6 dB, 17.9 dB, or 21.6 dB and low power in applications where a small package size is critical. 0.1 dB compression: 1000 mV p-p, 750 mV p-p, or 450 mV p-p The LNA has a single-ended to differential gain that is selectable Flexible active input impedance matching through the serial port interface (SPI). Assuming a 15 MHz Variable gain amplifier (VGA) noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA Attenuator range: 45 dB, linear in dB gain control input SNR is 94 dB. In CW Doppler mode, each LNA output Postamp gain (PGA): 21 dB, 24 dB, 27 dB, or 30 dB drives an I/Q demodulator that has independently Antialiasing filter (AAF) programmable phase rotation with 16 phase settings. Programmable second-order low-pass filter (LPF) from 8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass Power-down of individual channels is supported to increase filter (HPF) battery life for portable applications. Standby mode allows quick Analog-to-digital converter (ADC) power-up for power cycling. In CW Doppler operation, the SNR: 75 dB, 14 bits up to 125 MSPS VGA, AAF, and ADC are powered down. The ADC contains JESD204B Subclass 0 coded serial digital outputs features to maximize flexibility and minimize system cost, such CW Doppler mode harmonic rejection I/Q demodulator as a programmable clock, data alignment, and programmable Individual programmable phase rotation digital test pattern generation. The digital test patterns include Dynamic range per channel: 160 dBFS/Hz built-in fixed patterns, built-in pseudorandom patterns, and Close-in SNR: 156 dBc/Hz, 1 kHz offset, 3 dBFS input custom user-defined test patterns entered via the SPI. RF digital decimation by 2 and high-pass filter APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9675 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Outputs and Timing ..................................................... 29 Applications ....................................................................................... 1 Analog Test Tone Generation ................................................... 38 General Description ......................................................................... 1 CW Doppler Operation ............................................................. 39 Revision History ............................................................................... 2 Digital RF Decimator ..................................................................... 40 Functional Block Diagram .............................................................. 3 Vector Profile .............................................................................. 40 Specif icat ions ..................................................................................... 4 RF Decimator .............................................................................. 41 AC Specifications .......................................................................... 4 Digital Test Waveforms .............................................................. 41 Digital Specifications ................................................................... 7 Digital Block Power Saving Scheme ........................................ 42 Switching Specifications .............................................................. 9 Serial Port Interface (SPI) .............................................................. 43 Absolute Maximum Ratings .......................................................... 12 Hardware Interface ..................................................................... 43 Thermal Impedance ................................................................... 12 Memory Map .................................................................................. 45 ESD Caution ................................................................................ 12 Reading the Memory Map Table .............................................. 45 Pin Configuration and Function Descriptions ........................... 13 Recommended Start-Up Sequence .......................................... 45 Typical Performance Characteristics ........................................... 16 Memory Map Register Table ..................................................... 47 TGC Mode ................................................................................... 16 Memory Map Register Descriptions ........................................ 59 CW Doppler Mode ..................................................................... 20 Outline Dimensions ....................................................................... 60 Theory of Operation ...................................................................... 21 Ordering Guide .......................................................................... 60 TGC Operation ........................................................................... 21 REVISION HISTORY 1/16Revision A: Initial Version Rev. A Page 2 of 60