Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9681 FEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD Low power 8 ADC channels integrated into 1 package D0+A1 SERIAL AD9681 LVDS D0A1 110 mW per channel at 125 MSPS with scalable power D1+A1 SERIAL 14 options LVDS VIN+A1 D1A1 DIGITAL PIPELINE D0+A2 SERIALIZER VINA1 ADC SERIAL SNR: 74 dBFS (to Nyquist) SFDR: 90 dBc (to Nyquist) LVDS D0A2 14 VIN+A2 D1+A2 DNL: 0.8 LSB (typical) INL: 1.2 LSB (typical) DIGITAL PIPELINE SERIAL SERIALIZER VINA2 ADC LVDS D1A2 Crosstalk, worst adjacent channel, 70 MHz, 1 dBFS: 83 dB typical Serial LVDS (ANSI-644, default) 14 D0+D1 SERIAL VIN+D1 DIGITAL PIPELINE Low power, reduced signal option (similar to IEEE 1596.3) LVDS D0D1 SERIALIZER VIND1 ADC D1+D1 SERIAL Data and frame clock outputs 14 LVDS VIN+D2 D1D1 DIGITAL PIPELINE 650 MHz full power analog bandwidth D0+D2 SERIALIZER VIND2 ADC SERIAL LVDS D0D2 2 V p-p input voltage range VREF D1+D2 SERIAL SENSE LVDS 1.8 V supply operation D1D2 1V REF VCM1, VCM2 FCO+1, FCO+2 SELECT Serial port control FCO1, FCO2 GND Flexible bit orientation DCO+1, DCO+2 SERIAL PORT CLOCK INTERFACE MANAGEMENT DCO1, DCO2 Built-in and custom digital test pattern generation Programmable clock and data alignment Power-down and standby modes APPLICATIONS Medical imaging Figure 1. Communications receivers The ADC contains several features designed to maximize flexibility Multichannel data acquisition and minimize system cost, such as programmable clock and data GENERAL DESCRIPTION alignment and programmable digital test pattern generation. The The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital available digital test patterns include built-in deterministic and converter (ADC) with an on-chip sample-and-hold circuit that pseudorandom patterns, along with custom user-defined test is designed for low cost, low power, small size, and ease of use. patterns entered via the serial port interface (SPI). The device operates at a conversion rate of up to 125 MSPS and The AD9681 is available in an RoHS-compliant, 144-ball is optimized for outstanding dynamic performance and low CSP-BGA. It is specified over the industrial temperature range of power in applications where a small package size is critical. 40C to +85C. This product is protected by a U.S. patent. The ADC requires a single 1.8 V power supply and an LVPECL-/ PRODUCT HIGHLIGHTS CMOS-/LVDS-compatible sample rate clock for full performance 1. Small Footprint. Eight ADCs are contained in a small, operation. No external reference or driver components are 10 mm 10 mm package. required for many applications. 2. Low Power. The device dissipates 110 mW per channel at The AD9681 automatically multiplies the sample rate clock for 125 MSPS with scalable power options. the appropriate LVDS serial data rate. Data clock outputs (DCO1, 3. Ease of Use. Data clock outputs (DCO1, DCO2) operate DCO2) for capturing data on the output and frame clock outputs at frequencies of up to 500 MHz and support double data (FCO1, FCO2) for signaling a new output byte are provided. rate (DDR) operation. Individual channel power-down is supported, and the device 4. User Flexibility. SPI control offers a wide range of flexible typically consumes less than 2 mW when all channels are disabled. features to meet specific system requirements. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20132020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. RBIAS1, RBIAS2 CSB1, CSB2 SDIO/OLM SCLK/DTP SYNC CLK+ CLK 11537-200AD9681 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Power-Down Mode .......................... 24 Applications ...................................................................................... 1 Digital Outputs and Timing ..................................................... 25 General Description ......................................................................... 1 Output Test Modes .................................................................... 28 Simplified Functional Block Diagram ........................................... 1 Serial Port Interface (SPI) ............................................................. 29 Product Highlights ........................................................................... 1 Configuration Using the SPI .................................................... 29 Revision History ............................................................................... 2 Hardware Interface .................................................................... 30 Functional Block Diagram .............................................................. 3 Configuration Without the SPI ................................................ 30 Specifications .................................................................................... 4 SPI Accessible Features ............................................................. 30 DC Specifications ......................................................................... 4 Memory Map .................................................................................. 31 AC Specifications ......................................................................... 5 Reading the Memory Map Register Table .............................. 31 Digital Specifications ................................................................... 6 Memory Map .............................................................................. 32 Switching Specifications .............................................................. 7 Memory Map Register Descriptions ....................................... 35 Timing Specifications .................................................................. 8 Applications Information ............................................................. 38 Absolute Maximum Ratings ......................................................... 12 Design Guidelines ...................................................................... 38 Thermal Characteristics ............................................................ 12 Power and Ground Recommendations .................................. 38 ESD Caution................................................................................ 12 Board Layout Considerations ................................................... 38 Pin Configuration and Function Descriptions .......................... 13 Clock Stability Considerations ................................................. 39 Typical Performance Characteristics ........................................... 16 VCM ............................................................................................. 39 Equivalent Circuits ......................................................................... 19 Reference Decoupling................................................................ 39 Theory of Operation ...................................................................... 20 SPI Port ........................................................................................ 39 Analog Input Considerations ................................................... 20 Outline Dimensions ....................................................................... 40 Voltage Reference ....................................................................... 21 Ordering Guide .......................................................................... 40 Clock Input Considerations ...................................................... 22 REVISION HISTORY 3/2020Rev. C to Rev. D 12/2013Rev. 0 to Rev. A Change to Power Dissipation and Power-Down Mode Section .... 24 Changes to Ordering Guide .......................................................... 39 10/2015Rev. B to Rev. C 11/2013Revision 0: Initial Version Added Endnote 4, Table 4 Renumbered Sequentially ............... 7 Changes to Clock Input Options Section .................................... 23 Changes to Digital Outputs and Timing Section ....................... 27 2/2015Rev. A to Rev. B Changes to SYNC Timing Requirements Parameter, Table 5 ... 8 Changes to Figure 7 ........................................................................ 10 Changes to Figure 8 ........................................................................ 11 Changes to Table 8 ......................................................................... 13 Changed AD9515-x to AD9515 ................................................... 23 Changes to Digital Outputs and Timing Section and Table 11 .... 27 Rev. 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