14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter Data Sheet AD9683 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz A and IN AD9683 JESD204B 250 MSPS INTERFACE VIN+ CML, TX Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz A IN PIPELINE SERDOUT0 OUTPUTS 14-BIT ADC HIGH VIN SPEED and 250 MSPS SERIALIZERS VCM Total power consumption: 434 mW at 250 MSPS 1.8 V supply voltages CMOS Integer 1-to-8 input clock divider CONTROL DIGITAL PDWN REGISTERS INPUT Sample rates of up to 250 MSPS SYSREF Intermediate frequency (IF) sampling frequencies of up to SYNCINB CLOCK CLK GENERATION 400 MHz RFCLK Internal analog-to-digital converter (ADC) voltage reference CMOS CMOS DIGITAL FAST DIGITAL FD INPUT/OUTPUT DETECT Flexible analog input range OUTPUT 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) RST SDIO SCLK CS Serial port control Figure 1. Energy saving power-down modes GENERAL DESCRIPTION APPLICATIONS The AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 supports communications applications Communications where low cost, small size, wide bandwidth, and versatility are Diversity radio systems desired. Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE The ADC core features a multistage, differential pipelined DOCSIS 3.0 CMTS upstream receive paths architecture with integrated output error correction logic. The HFC digital reverse path receivers ADC core features wide bandwidth inputs supporting a variety Smart antenna systems of user-selectable input ranges. An integrated voltage reference Electronic test and measurement equipment eases design considerations. A duty cycle stabilizer (DCS) is Radar receivers provided to compensate for variations in the ADC clock duty cycle, COMSEC radio architectures allowing the converter to maintain excellent performance. The IED detection/jamming systems JESD204B high speed serial interface reduces board routing General-purpose software radios requirements and lowers pin count requirements for the Broadband data applications receiving device. Ultrasound equipment The ADC output data is routed directly to the JESD204B serial output lane. These outputs are at CML voltage levels. Data can be sent through the lane at the maximum sampling rate of 250 MSPS, which results in a lane rate of 5 Gbps. Synchronization inputs (SYNCINB and SYSREF) are provided. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11410-001AD9683 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Standby Mode .................................... 23 Applications ....................................................................................... 1 Digital Outputs ............................................................................... 24 Functional Block Diagram .............................................................. 1 JESD204B Transmit Top Level Description ............................ 24 General Description ......................................................................... 1 ADC Overrange and Gain Control .......................................... 29 Revision History ............................................................................... 2 DC Correction (DCC) ................................................................... 31 Product Highlights ........................................................................... 3 DC Correction Bandwidth ........................................................ 31 Specifications ..................................................................................... 4 DC Correction Readback .......................................................... 31 ADC DC Specifications ............................................................... 4 DC Correction Freeze ................................................................ 31 ADC AC Specifications ............................................................... 5 DC Correction Enable Bits ....................................................... 31 Digital Specifications ................................................................... 6 Serial Port Interface (SPI) .............................................................. 32 Switching Specifications .............................................................. 8 Configuration Using the SPI ..................................................... 32 Timing Specifications .................................................................. 9 Hardware Interface ..................................................................... 32 Absolute Maximum Ratings .......................................................... 10 SPI Accessible Features .............................................................. 33 Thermal Characteristics ............................................................ 10 Memory Map .................................................................................. 34 ESD Caution ................................................................................ 10 Reading the Memory Map Register Table ............................... 34 Pin Configuration and Function Descriptions ........................... 11 Memory Map Register Table ..................................................... 35 Typical Performance Characteristics ........................................... 13 Memory Map Register Descriptions ........................................ 39 Equivalent Circuits ......................................................................... 18 Applications Information .............................................................. 43 Theory of Operation ...................................................................... 19 Design Guidelines ...................................................................... 43 ADC Architecture ...................................................................... 19 Outline Dimensions ....................................................................... 44 Analog Input Considerations .................................................... 19 Ordering Guide .......................................................................... 44 Voltage Reference ....................................................................... 20 Clock Input Considerations ...................................................... 21 REVISION HISTORY 6/2016Rev. C to Rev.D Changes to SYNCINB+ Pin Description .................................... 11 Changes to Table 17 ........................................................................ 37 Changes to Transfer Register Map Section ................................. 34 Change to JESD204B Link Control 1 (Address 0x5F) Section ....... 40 Changes to Register 0x3A ............................................................. 36 Changes to Register 0x6F, Register 0x70, Register 0x72, 9/2015Rev. B to Rev. C Register 0x73, Register 0x74, Register 0x75 ................................ 38 Changes to General Description Section ...................................... 3 Changes to JESD204B Link Control 2 (Address 0x60) Section ..... 40 Changes to Nyquist Clock Input Options Section ..................... 21 Changes to JESD204B Overview Section .................................... 24 2/2014Rev. 0 to Rev. A Changes to Figure 60 ...................................................................... 27 Changes to Data Output Parameters, Table 4 ................................ 8 Change to Table 17 ......................................................................... 37 Changes to Figure 3 ........................................................................... 9 4/2013Revision 0: Initial Version 5/2014Rev. A to Rev. B Changed Minimum RF Clock Rate from 625 MHz to 500 MHz (Throughout) .................................................................................... 6 Rev. D Page 2 of 44