14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter Data Sheet AD9684 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 DVDD DRVDD SPIVDD Parallel LVDS (DDR) outputs (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.8V TO 3.4V) 1.1 W total power per channel at 500 MSPS (default settings) BUFFER VIN+A SFDR = 85 dBFS at 170 MHz f (500 MSPS) IN 14 ADC D0 D1 CORE SNR = 68.6 dBFS at 170 MHz f (500 MSPS) VINA D2 IN DIGITAL D3 DOWN- D4 ENOB = 10.9 bits at 170 MHz f CONVERTER IN D5 16 FD A D6 D7 DNL = 0.5 LSB D8 D9 INL = 2.5 LSB D10 FD B D11 DIGITAL D12 Noise density = 153 dBFS/Hz at 500 MSPS DOWN- D13 CONVERTER DCO BUFFER 1.25 V, 2.50 V, and 3.3 V supply operation STATUS VIN+B 14 ADC No missing codes CORE CONTROL VINB REGISTERS Internal analog-to-digital converter (ADC) voltage reference FAST DETECT V 1P0 Flexible input range and termination impedance SYNC+ SIGNAL MONITOR CLOCK 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) GENERATION SYNC CLK+ 400 , 200 , 100 , and 50 differential SPI CONTROL CLK SYNC input allows multichip synchronization 2 PDWN/ STBY 4 DDR LVDS (ANSI-644 levels) outputs AD9684 8 2 GHz usable analog input full power bandwidth >96 dB channel isolation/crosstalk AGND DRGND DGND SDIO SCLK CSB Amplitude detect bits for efficient AGC implementation Figure 1. Two integrated wideband digital processors per channel GENERAL DESCRIPTION 12-bit numerically controlled oscillator (NCO) The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has 3 cascaded half-band filters an on-chip buffer and a sample-and-hold circuit designed for Differential clock inputs low power, small size, and ease of use. This product is designed Serial port control for sampling wide bandwidth analog signals. The AD9684 is Integer clock divide by 2, 4, or 8 optimized for wide input bandwidth, a high sampling rate, Small signal dither excellent linearity, and low power in a small package. APPLICATIONS The dual ADC cores feature a multistage, differential pipelined Communications architecture with integrated output error correction logic. Each Diversity multiband, multimode digital receivers ADC features wide bandwidth buffered inputs, supporting a 3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE variety of user selectable input ranges. An integrated voltage General-purpose software radios reference eases design considerations. Each ADC data output is Ultrawideband satellite receiver internally connected to an optional decimate by 2 block. Instrumentation (spectrum analyzers, network analyzers, The analog input and clock signals are differential inputs. Each integrated RF test solutions) ADC data output is internally connected to two digital Radar downconverters (DDCs). Each DDC consists of four cascaded Digital oscilloscopes signal processing stages: a 12-bit frequency translator (NCO), High speed data acquisition systems and three half-band decimation filters supporting a divide by DOCSIS CMTS upstream receiver paths factor of two, four, and eight. HFC digital reverse path receivers Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com FAST DETECT SIGNAL MONITOR LVDS OUTPUT STAGING LVDS OUTPUTS LVDS/SYNC CONTROL 13015-001AD9684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC I/Q Output Selection ....................................................... 31 Applications ....................................................................................... 1 DDC General Description ........................................................ 31 Functional Block Diagram .............................................................. 1 Frequency Translation ................................................................... 37 General Description ......................................................................... 1 General Description ................................................................... 37 Revision History ............................................................................... 2 DDC NCO Plus Mixer Loss and SFDR ................................... 38 Product Highlights ........................................................................... 3 Numerically Controlled Oscillator .......................................... 38 Specifications ..................................................................................... 4 FIR Filters ........................................................................................ 40 DC Specifications ......................................................................... 4 General Description ................................................................... 40 AC Specifications .......................................................................... 5 Half-Band Filters ........................................................................ 41 Digital Specifications ................................................................... 6 DDC Gain Stage ......................................................................... 42 Switching Specifications .............................................................. 7 DDC Complex to Real Conversion Block............................... 42 Timing Specifications .................................................................. 8 DDC Example Configurations ................................................. 43 Absolute Maximum Ratings .......................................................... 16 Digital Outputs ............................................................................... 47 Thermal Characteristics ............................................................ 16 Digital Outputs ........................................................................... 47 ESD Caution ................................................................................ 16 ADC Overrange .......................................................................... 47 Pin Configuration and Function Descriptions ........................... 17 Multichip Synchronization ............................................................ 48 Typical Performance Characteristics ........................................... 19 SYNC Setup and Hold Window Monitor ............................. 49 Equivalent Circuits ......................................................................... 22 Test Modes ....................................................................................... 51 Theory of Operation ...................................................................... 24 ADC Test Modes ........................................................................ 51 ADC Architecture ...................................................................... 24 Serial Port Interface (SPI) .............................................................. 52 Analog Input Considerations .................................................... 24 Configuration Using the SPI ..................................................... 52 Voltage Reference ....................................................................... 26 Hardware Interface ..................................................................... 52 Clock Input Considerations ...................................................... 27 SPI Accessible Features .............................................................. 52 Power-Down/Standby Mode..................................................... 28 Memory Map .................................................................................. 53 Temperature Diode .................................................................... 28 Reading the Memory Map Register Table ............................... 53 ADC Overrange and Fast Detect .................................................. 29 Memory Map Register Table ..................................................... 54 ADC Overrange .......................................................................... 29 Applications Information .............................................................. 63 Fast Threshold Detection (FD A and FD B) ........................ 29 Power Supply Recommendations ............................................. 63 Signal Monitor ................................................................................ 30 Outline Dimensions ....................................................................... 64 Digital Downconverters (DDCs) .................................................. 31 Ordering Guide .......................................................................... 64 DDC I/Q Input Selection .......................................................... 31 REVISION HISTORY 5/15Revision 0: Initial Version Rev. 0 Page 2 of 64