14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9691 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD SR DVDD DRVDD SPIVDD JESD204B (Subclass 1) coded serial digital outputs (1.25V) (2.50V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 1.9 W total power per channel (default settings) BUFFER VIN+A ADC SFDR = 77 dBFS at 340 MHz 14 CORE DIGITAL VINA SERDOUT0 DOWN- SNR = 63.4 dBFS at 340 MHz (A = 1.0 dBFS) IN SERDOUT1 CONVERTER FD A 8 SERDOUT2 Noise density = 152.6 dBFS/Hz SERDOUT3 SIGNAL SERDOUT4 MONITOR SERDOUT5 1.25 V, 2.50 V, and 3.3 V dc supply operation DIGITAL SERDOUT6 FD B DOWN- SERDOUT7 14 No missing codes CONVERTER VIN+B ADC CORE VINB 1.58 V p-p differential full scale input voltage CONTROL BUFFER REGISTERS Flexible termination impedance FAST DETECT V 1P0 400 , 200 , 100 , and 50 differential AD9691 SIGNAL SYNCINB MONITOR JESD204B CLOCK 1.5 GHz usable analog input full power bandwidth SUBCLASS 1 GENERATION CONTROL SYSREF 95 dB channel isolation/crosstalk CLK+ CLK 2 SPI CONTROL PDWN/ Amplitude detection bits for efficient AGC implementation 4 STBY 8 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 cascaded half-band filters AGND DRGND DGND SDIO SCLK CSB Figure 1. Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Timestamp feature Small signal dither APPLICATIONS Communications (wideband receivers and digital predistortion) this threshold indicator has low latency, the user can quickly Instrumentation (spectrum analyzers, network analyzers, turn down the system gain to avoid an overrange condition at integrated RF test solutions) the ADC input. DOCSIS 3.x CMTS upstream receive paths High speed data acquisition systems Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane GENERAL DESCRIPTION configurations, depending on the DDC configuration and the The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter acceptable lane rate of the receiving logic device. Multiple device (ADC). The device has an on-chip buffer and sample-and-hold synchronization is supported through the SYSREF input pins. circuit designed for low power, small size, and ease of use. The The AD9691 is available in a Pb-free, 88-lead LFCSP and is device is designed for sampling wide bandwidth analog signals specified over the 40C to +85C industrial temperature range. of up to 1.5 GHz. This product is protected by a U.S. patent. The dual ADC cores feature a multistage, differential pipelined PRODUCT HIGHLIGHTS architecture with integrated output error correction logic. Each 1. Low power consumption analog core, 14-bit, 1.25 GSPS ADC features wide bandwidth inputs supporting a variety of dual ADC with 1.9 W per channel. user-selectable input ranges. An integrated voltage reference 2. Wide full power bandwidth supports intermediate eases design considerations. frequency (IF) sampling of signals up to 1.5 GHz. Each ADC data output is internally connected to two digital 3. Buffered inputs with programmable input termination downconverters (DDCs). Each DDC consists of four cascaded eases filter design and implementation. signal processing stages: a 12-bit frequency translator (NCO) 4. Flexible serial port interface (SPI) controls various product and four half-band decimation filters. features and functions to meet specific system requirements. In addition to the DDC blocks, the AD9691 has a programmable 5. Programmable fast overrange detection. threshold detector that allows monitoring of the incoming 6. 12 mm 12 mm, 88-lead LFCSP. signal power using the fast detect output bits of the ADC. Because Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com FAST DETECT JESD204B HIGH SPEED SERIALIZER Tx OUTPUTS 13092-001AD9691 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC NCO Plus Mixer Loss and SFDR ................................... 34 Applications ....................................................................................... 1 Numerically Controlled Oscillator .......................................... 34 General Description ......................................................................... 1 FIR Filters ........................................................................................ 36 Functional Block Diagram .............................................................. 1 General Description ................................................................... 36 Product Highlights ........................................................................... 1 Half-Band Filters ........................................................................ 37 Revision History ............................................................................... 2 DDC Gain Stage ......................................................................... 39 Specifications ..................................................................................... 3 DDC Complex to Real Conversion Block............................... 39 DC Specifications ......................................................................... 3 DDC Example Configurations ................................................. 40 AC Specifications .......................................................................... 4 Digital Outputs ............................................................................... 43 Digital Specifications ................................................................... 5 Introduction to the JESD204B Interface ................................. 43 Switching Specifications .............................................................. 6 JESD204B Overview .................................................................. 43 Timing Specifications .................................................................. 7 Functional Overview ................................................................. 44 Absolute Maximum Ratings ............................................................ 9 JESD204B Link Establishment ................................................. 45 Thermal Characteristics .............................................................. 9 Physical Layer (Driver) Outputs .............................................. 47 ESD Caution .................................................................................. 9 Configuring the JESD204B Link .............................................. 48 Pin Configuration and Function Descriptions ........................... 10 Multichip Synchronization ............................................................ 51 Typical Performance Characteristics ........................................... 12 SYSREF Setup/Hold Window Monitor ................................. 52 Equivalent Circuits ......................................................................... 16 Test Modes ....................................................................................... 54 Theory of Operation ...................................................................... 18 ADC Test Modes ........................................................................ 54 ADC Architecture ...................................................................... 18 JESD204B Block Test Modes .................................................... 54 Analog Input Considerations .................................................... 18 Serial Port Interface ........................................................................ 57 Voltage Reference ....................................................................... 20 Configuration Using the SPI ..................................................... 57 Clock Input Considerations ...................................................... 21 Hardware Interface ..................................................................... 57 Power-Down/Standby Mode .................................................... 22 SPI Accessible Features .............................................................. 57 Temperature Diode .................................................................... 22 Memory Map .................................................................................. 58 ADC Overrange and Fast Detect .................................................. 23 Reading the Memory Map Register Table ............................... 58 ADC Overrange .......................................................................... 23 Memory Map Register Table ..................................................... 59 Fast Threshold Detection (FD A and FD B) ........................ 23 Applications Information .............................................................. 71 Signal Monitor ................................................................................ 24 Power Supply Recommendations ............................................. 71 Digital Downconverters (DDCs) .................................................. 27 Exposed Pad Thermal Heat Slug Recommendations ............ 71 DDC I/Q Input Selection .......................................................... 27 AVDD1 SR (Pin 78) and AGND (Pin 77 and Pin 81) .............. 71 DDC I/Q Output Selection ....................................................... 27 Outline Dimensions ....................................................................... 72 DDC General Description ........................................................ 27 Ordering Guide .......................................................................... 72 Frequency Translation ................................................................... 33 General Description ................................................................... 33 REVISION HISTORY 7/15Revision 0: Initial Version Rev. 0 Page 2 of 72