14-Bit, 500 MSPS, JESD204B, Quad Analog-to-Digital Converter Data Sheet AD9694 FEATURES Amplitude detect bits for efficient AGC implementation 4 integrated wideband digital processors JESD204B (Subclass 1) coded serial digital outputs 48-bit NCO, up to 4 cascaded half-band filters Lane rates up to 15 Gbps Differential clock input 1.66 W total power at 500 MSPS Integer clock divide by 1, 2, 4, or 8 415 mW per ADC channel On-chip temperature diode SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)S Flexible JESD204B lane configurations SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range) Noise density = 151.5 dBFS/Hz (1.80 V p-p input range) APPLICATIONS 0.975 V, 1.8 V, and 2.5 V dc supply operation Communications No missing codes Diversity multiband, multimode digital receivers Internal ADC voltage reference 3G/4G, W-CDMA, GSM, LTE, LTE-A Analog input buffer General-purpose software radios On-chip dithering to improve small signal linearity Ultrawideband satellite receivers Flexible differential input range Instrumentation 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal) Radars 1.4 GHz analog input full power bandwidth Signals intelligence (SIGINT) FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD1 SR AVDD2 AVDD3 DVDD DRVDD1 DRVDD2 SPIVDD (1.8V) (0.975V) (0.975V) (2.5V) (0.975V) (0.975V) (1.8V) (1.8V) BUFFER 14 DIGITAL DOWN VIN+A ADC CONVERTER CORE (DDC) VINA 2 VCM AB JESD204B SERDOUTAB0 Tx HIGH SPEED FD A FAST SIGNAL OUTPUTS SERIALIZER SERDOUTAB1 DETECT MONITOR FD B BUFFER 14 DIGITAL DOWN VIN+B ADC CONVERTER CORE (DDC) VINB SIGNAL MONITOR AND FAST DETECT SYSREF JESD204B CLOCK SUBCLASS 1 CLK+ GENERATION SYNCINBAB CONTROL SYNCINBCD 2 CLK 4 8 BUFFER 14 DIGITAL DOWN- VIN+C ADC CONVERTER CORE (DDC) VINC 2 VCM CD/VREF JESD204B Tx SERDOUTCD0 HIGH SPEED FD C FAST SIGNAL OUTPUTS SERDOUTCD1 SERIALIZER DETECT MONITOR FD D BUFFER 14 DIGITAL DOWN- VIN+D ADC CONVERTER CORE (DDC) VIND SPI CONTROL PDWN/STBY AD9694 AGND SR AGND DRGND SDIO SCLK CSB Figure 1. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 14808-001AD9694 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Half-Band Filters ........................................................................ 43 Applications ....................................................................................... 1 DDC Gain Stage ......................................................................... 44 Functional Block Diagram .............................................................. 1 DDC Complex to Real Conversion ......................................... 44 Revision History ............................................................................... 3 DDC Example Configurations ................................................. 45 General Description ......................................................................... 4 Digital Outputs ............................................................................... 50 Product Highlights ........................................................................... 4 Introduction to the JESD204B Interface ................................. 50 Specifications ..................................................................................... 5 Setting Up the AD9694 Digital Interface ................................ 50 DC Specifications ......................................................................... 5 Functional Overview ................................................................. 52 AC Specifications .......................................................................... 6 JESD204B Link Establishment ................................................. 52 Digital Specifications ................................................................... 9 Physical Layer (Driver) Outputs .............................................. 53 Switching Specifications ............................................................ 10 JESD204B Tx Converter Mapping ........................................... 54 Timing Specifications ................................................................ 11 Configuring the JESD204B Link .............................................. 56 Absolute Maximum Ratings .......................................................... 12 Latency ............................................................................................. 60 Thermal Resistance .................................................................... 12 End to End Total Latency .......................................................... 60 ESD Caution ................................................................................ 12 Example Latency Calculations.................................................. 60 Pin Configuration and Function Descriptions ........................... 13 LMFC referenced Latency ......................................................... 60 Typical Performance Characteristics ........................................... 15 Deterministic Latency .................................................................... 61 Equivalent Circuits ......................................................................... 22 Subclass 0 Operation .................................................................. 61 Theory of Operation ...................................................................... 24 Subclass 1 Operation .................................................................. 61 ADC Architecture ...................................................................... 24 Multichip Synchronization ............................................................ 63 Analog Input Considerations .................................................... 24 Normal Mode .............................................................................. 63 Voltage Reference ....................................................................... 25 Timestamp Mode ....................................................................... 63 DC Offset Calibration ................................................................ 26 SYSREF Input ........................................................................... 65 Clock Input Considerations ...................................................... 26 SYSREF Setup/Hold Window Monitor ................................. 66 ADC Overrange and Fast Detect .................................................. 29 Test Modes ....................................................................................... 68 ADC Overrange .......................................................................... 29 ADC Test Modes ........................................................................ 68 Fast Threshold Detection (FD A, FD B, FD C, and JESD204B Block Test Modes .................................................... 69 FD D) .......................................................................................... 29 Serial Port Interface ........................................................................ 71 Signal Monitor ................................................................................ 30 Configuration Using the SPI ..................................................... 71 SPORT Over JESD204B ............................................................. 30 Hardware Interface ..................................................................... 71 Digital Downconverter (DDC) ..................................................... 33 SPI Accessible Features .............................................................. 71 DDC I/Q Input Selection .......................................................... 33 Memory Map .................................................................................. 72 DDC I/Q Output Selection ....................................................... 33 Reading the Memory Map Register Table ............................... 72 DDC General Description ........................................................ 33 Memory Map Register TableDetails .................................... 73 Frequency Translation ................................................................... 39 Applications Information .............................................................. 95 Overview ...................................................................................... 39 Power Supply Recommendations ............................................. 95 DDC NCO and Mixer Loss and SFDR .................................... 40 Exposed Pad Thermal Heat Slug Recommendations ............ 95 Numerically Controlled Oscillator ........................................... 40 AVDD1 SR (Pin 64) and AGND SR (Pin 63 and Pin 67) ... 95 FIR Filters ........................................................................................ 42 Outline Dimensions ....................................................................... 96 Overview ...................................................................................... 42 Ordering Guide .......................................................................... 96 Rev. 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