14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9695 FEATURES APPLICATIONS JESD204B (Subclass 1) coded serial digital outputs Communications Lane rates up to 16 Gbps Diversity multiband, multimode digital receivers 1.6 W total power at 1300 MSPS 3G/4G, TD-SCDMA, WCDMA, GSM, LTE 800 mW per ADC channel General-purpose software radios SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range) Ultrawideband satellite receiver SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range) Instrumentation Noise density Oscilloscopes 153.9 dBFS/Hz (1.59 V p-p input range) Spectrum analyzers 155.6 dBFS/Hz (2.04 V p-p input range) Network analyzers 0.95 V, 1.8 V, and 2.5 V supply operation Integrated RF test solutions No missing codes Radars Internal ADC voltage reference Electronic support measures, electronic counter measures, Flexible input range and electronic counter-counter measures 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) High speed data acquisition systems 2 GHz usable analog input full power bandwidth DOCSIS 3.0 CMTS upstream receive paths >95 dB channel isolation/crosstalk Hybrid fiber coaxial digital reverse path receivers Amplitude detect bits for efficient AGC implementation Wideband digital predistortion 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD1 DRVDD2 SPIVDD (0.95V) (1.8V) (2.5V) (0.95V) (0.95V) (0.95V) (1.8V) (1.8V) BUFFER 14 VIN+A ADC CORE VINA DIGITAL DOWN- CONVERTER JESD204B SERDOUT0 4 LINK FAST SIGNAL SERDOUT1 AND DETECT MONITOR SERDOUT2 Tx DIGITAL DOWN- SERDOUT3 OUTPUTS CONVERTER 14 VIN+B ADC VINB CORE BUFFER VREF SYNCINB PDWN/STBY JESD204B CLOCK SUBCLASS 1 SYSREF DISTRIBUTION CONTROL FD A/GPIO A0 GPIO MUX CLK+ SPI AND FD B/GPIO B0 CONTROL REGISTERS CLK 2 AD9695 4 AGND SDIO SCLK CSB DRGND DGND Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20172020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. PROGRAMMABLE FIR FILTER CROSSBAR MUX CROSSBAR MUX 15660-001AD9695 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC General Description ........................................................ 42 Applications ...................................................................................... 1 DDC Frequency Translation .................................................... 45 Functional Block Diagram .............................................................. 1 DDC Decimation Filters ........................................................... 53 Revision History ............................................................................... 3 DDC Gain Stage ......................................................................... 60 General Description ......................................................................... 4 DDC Complex to Real Conversion ......................................... 61 Product Highlights ........................................................................... 4 DDC Mixed Decimation Settings ............................................ 62 Specifications .................................................................................... 5 DDC Example Configurations ................................................. 64 DC Specifications ......................................................................... 5 DDC Power Consumption ....................................................... 67 AC Specifications1300 MSPS ................................................. 6 Signal Monitor ................................................................................ 68 AC Specifications625 MSPS ................................................... 8 SPORT Over JESD204B ............................................................ 69 Digital Specifications ................................................................... 9 Digital Outputs ............................................................................... 71 Switching Specifications ............................................................ 10 Introduction to the JESD204B Interface ................................. 71 Timing Specifications ................................................................ 11 JESD204B Overview .................................................................. 71 Absolute Maximum Ratings ......................................................... 13 Functional Overview ................................................................. 72 Thermal Characteristics ............................................................ 13 JESD204B Link Establishment ................................................. 72 ESD Caution................................................................................ 13 Physical Layer (Driver) Outputs .............................................. 74 Pin Configuration and Function Descriptions .......................... 14 Setting Up the AD9695 Digital Interface ................................ 75 Typical Performance Characteristics ........................................... 16 Deterministic Latency .................................................................... 81 1300 MSPS ................................................................................... 16 Subclass 0 Operation ................................................................. 81 625 MSPS ..................................................................................... 21 Subclass 1 Operation ................................................................. 81 Equivalent Circuits ......................................................................... 25 Multichip Synchronization ........................................................... 83 Theory of Operation ...................................................................... 27 Normal Mode ............................................................................. 83 ADC Architecture ...................................................................... 27 Timestamp Mode ....................................................................... 83 Analog Input Considerations ................................................... 27 SYSREF Input ........................................................................... 85 Voltage Reference ....................................................................... 30 SYSREF Setup/Hold Window Monitor ................................ 87 DC Offset Calibration ................................................................ 30 Latency ............................................................................................. 89 Clock Input Considerations ...................................................... 30 End to End Total Latency ......................................................... 89 Power-Down/Standby Mode .................................................... 33 Example Latency Calculations ................................................. 89 Temperature Diode .................................................................... 33 LMFC Referenced Latency ....................................................... 89 ADC Overrange and Fast Detect .................................................. 34 Test Modes ...................................................................................... 91 ADC Overrange .......................................................................... 34 ADC Test Modes ........................................................................ 91 Fast Threshold Detection (FD A and FD B) ........................ 34 JESD204B Block Test Modes .................................................... 92 ADC Application Modes and JESD204B Tx Converter Serial Port Interface (SPI) ............................................................. 94 Mapping ........................................................................................... 35 Configuration Using the SPI .................................................... 94 Programmable Finite Impulse Response (FIR) Filters .............. 37 Hardware Interface .................................................................... 94 Supported Modes ....................................................................... 37 SPI Accessible Features ............................................................. 94 Programming Instructions ....................................................... 39 Memory Map .................................................................................. 95 Digital Downconverter (DDC) ..................................................... 42 Reading the Memory Map Register Table .............................. 95 DDC I/Q Input Selection .......................................................... 42 Memory Map Registers ............................................................. 96 DDC I/Q Output Selection ....................................................... 42 Applications Information ........................................................... 134 Rev. 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