8-/10-/12-/14-Bit, 175 MSPS TxDAC Digital-to-Analog Converters Data Sheet AD9704/AD9705/AD9706/AD9707 The AD9704/AD9705/AD9706/AD9707 has an optional serial FEATURES peripheral interface (SPI) that provides a higher level of program- 175 MSPS update rate mability to enhance performance of the DAC. An adjustable Low power member of pin-compatible output, common-mode feature allows for easy interfacing to other TxDAC product family components that require common modes from 0 V to 1.2 V. Low power dissipation Edge-triggered input latches and a 1.0 V temperature-compensated 12 mW at 80 MSPS, 1.8 V band gap reference have been integrated to provide a complete, 50 mW at 175 MSPS, 3.3 V monolithic DAC solution. The digital inputs support 1.8 V and Wide supply voltage: 1.7 V to 3.6 V 3.3 V CMOS logic families. SFDR to Nyquist AD9707: 84 dBc at 5 MHz output PRODUCT HIGHLIGHTS AD9707: 83 dBc at 10 MHz output 1. Pin Compatible. The AD9704/AD9705/AD9706/AD9707 AD9707: 75 dBc at 20 MHz output line of TxDAC converters is pin-compatible with the Adjustable full-scale current outputs: 1 mA to 5 mA AD9748/AD9740/AD9742/AD9744 TxDAC line On-chip 1.0 V reference (LFCSP VQ package). CMOS-compatible digital interface 2. Low Power. Complete CMOS DAC operates on a single Common-mode output: adjustable 0 V to 1.2 V supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) Power-down mode <2 mW at 3.3 V (SPI controllable) and 12 mW (1.8 V). The DAC full-scale current can be Self-calibration reduced for lower power operation. Sleep and power-down Compact 32-lead LFCSP VQ, RoHS compliant package modes are provided for low power idle periods. GENERAL DESCRIPTION 3. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. The AD9704/AD9705/AD9706/AD9707 are the fourth-generation 4. Twos Complement/Binary Data Coding Support. Data family in the TxDAC series of high performance, CMOS digital-to- input supports twos complement or straight binary data analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit coding. resolution family is optimized for low power operation, while 5. Flexible Clock Input. A selectable high speed, single-ended, maintaining excellent dynamic performance. The AD9704/ and differential CMOS clock input supports 175 MSPS AD9705/AD9706/AD9707 family is pin-compatible with the conversion rate. AD9748/AD9740/AD9742/AD9744 family of TxDAC converters 6. Device Configuration. Device can be configured through and is specifically optimized for the transmit signal path of pin strapping, and SPI control offers a higher level of communication systems. All of the devices share the same programmability. interface, LFCSP VQ package, and pinout, providing an upward or 7. Easy Interfacing to Other Components. Adjustable downward component selection path based on performance, common-mode output allows for easy interfacing to other resolution, and cost. The AD9704/AD9705/AD9706/AD9707 signal chain components that accept common-mode levels offers exceptional ac and dc performance, while supporting from 0 V to 1.2 V. update rates up to 175 MSPS. 8. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/ The flexible power supply operating range of 1.7 V to 3.6 V and low AD9707 include a 1.0 V temperature-compensated band power dissipation of the AD9704/AD9705/AD9706/AD9707 parts gap voltage reference. make them well suited for portable and low power applications. 9. Industry-Standard 32-Lead LFCSP VQ Package. Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW. Rev. 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Technical Support www.analog.com AD9704/AD9705/AD9706/AD9707 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 29 General Description ......................................................................... 1 Theory of Operation ...................................................................... 30 Product Highlights ........................................................................... 1 Serial Peripheral Interface ......................................................... 30 Revision History ............................................................................... 2 SPI Register Map ........................................................................ 32 Functional Block Diagram .............................................................. 4 SPI Register Descriptions .......................................................... 33 Specifications ..................................................................................... 5 Reference Operation .................................................................. 34 DC Specifications (3.3 V) ............................................................ 5 Reference Control Amplifier .................................................... 34 Dynamic Specifications (3.3 V) .................................................. 6 DAC Transfer Function ............................................................. 35 Digital Specifications (3.3 V) ...................................................... 7 Analog Outputs .......................................................................... 35 DC Specifications (1.8 V) ............................................................ 8 Adjustable Output Common Mode ......................................... 36 Dynamic Specifications (1.8 V) .................................................. 9 Digital Inputs .............................................................................. 36 Digital Specifications (1.8 V) .................................................... 10 Clock Input.................................................................................. 36 Timing Diagram ......................................................................... 10 DAC Timing ................................................................................ 36 Absolute Maximum Ratings .......................................................... 11 Power Dissipation....................................................................... 37 Thermal Characteristics ............................................................ 11 Self-Calibration ........................................................................... 38 ESD Caution ................................................................................ 11 Applications Information .............................................................. 40 Pin Configurations and Function Descriptions ......................... 12 Output Configurations .............................................................. 40 AD9707 ........................................................................................ 12 Differential Coupling Using a Transformer ............................... 40 AD9706 ........................................................................................ 13 Single-Ended Buffered Output Using an Op Amp ................ 40 AD9705 ........................................................................................ 14 Differential Buffered Output Using an Op Amp ................... 41 AD9704 ........................................................................................ 15 Evaluation Board ........................................................................ 41 Typical Performance Characteristics ........................................... 16 Outline Dimensions ....................................................................... 42 AD9707 ........................................................................................ 16 Ordering Guide .......................................................................... 42 AD9704, AD9705, and AD9706 ............................................... 23 REVISION HISTORY 9/2017Rev. B to Rev. C Changes to Figure 5 and Table 11................................................. 14 Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Figure 6 and Table 12................................................. 15 Changes to Table 9 .......................................................................... 12 Changes to Figure 15 and Figure 16 ............................................ 17 Changes to Table 10 ........................................................................ 13 Moved Figure 41 to Figure 24 Position........................................ 18 Changes to Table 11 ........................................................................ 14 Moved Figure 42 to Figure 25 Position and Moved Figure 43 to Changes to Table 12 ........................................................................ 15 Figure 26 Position ........................................................................... 19 Changes to Reference Operation Section .................................... 34 Changes to Figure 27 ...................................................................... 20 Updated Outline Dimensions ....................................................... 42 Changes to Figure 33 to Figure 35 ................................................ 21 Changes to Ordering Guide .......................................................... 42 Moved Figure 24 to Figure 41 Position........................................ 22 Moved Figure 25 to Figure 43 Position and Moved Figure 26 to 10/2011Rev. A to Rev. B Figure 44 Position ........................................................................... 23 Changes to Features Section............................................................ 1 Changes to Figure 44 ...................................................................... 23 Changes to Table 1 ............................................................................ 5 Changes to Figure 57 ...................................................................... 26 Changes to Table 2 ............................................................................ 6 Changes to Figure 70 ...................................................................... 29 Changes to Table 4 ............................................................................ 8 Changes to Serial Peripheral Interface Section .......................... 30 Changes to Table 5 ............................................................................ 9 Changes to Table 15 ....................................................................... 32 Changes to Figure 3 and Table 9 ................................................... 12 Deleted Table 23 Renumbered Sequentially .............................. 33 Changes to Figure 4 and Table 10 ................................................. 13 Rev. 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