8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter AD9709 FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD1/ DCOM1/ 8-bit dual transmit digital-to-analog converter (DAC) DVDD2 DCOM2 AVDD ACOM CLK1 125 MSPS update rate I OUTA1 1 1 Excellent SFDR to Nyquist 5 MHz output: 66 dBc PORT1 LATCH DAC I OUTB1 Excellent gain and offset matching: 0.1% REFIO Fully independent or single-resistor gain control FSADJ1 REFERENCE WRT1/IQWRT FSADJ2 Dual port or interleaved data DIGITAL AD9709 GAINCTRL INTERFACE WRT2/IQSEL On-chip 1.2 V reference BIAS SLEEP GENERATOR Single 5 V or 3.3 V supply operation I Power dissipation: 380 mW 5 V 2 2 OUTA2 PORT2 LATCH DAC I Power-down mode: 50 mW 5 V OUTB2 48-lead LQFP MODE CLK2/IQ RESET Figure 1. APPLICATIONS Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound glitch energy and to maximize dynamic accuracy. Each DAC GENERAL DESCRIPTION provides differential current output, thus supporting single- 1 The AD9709 is a dual-port, high speed, 2-channel, 8-bit CMOS ended or differential applications. Both DACs can be DAC. It integrates two high quality 8-bit TxDAC+ cores, a voltage simultaneously updated and provide a nominal full-scale reference, and digital interface circuitry into a small 48-lead LQFP current of 20 mA. The full-scale currents between each DAC package. The AD9709 offers exceptional ac and dc performance are matched to within 0.1%. while supporting update rates of up to 125 MSPS. The AD9709 is manufactured on an advanced low-cost CMOS The AD9709 has been optimized for processing I and Q data in process. It operates from a single supply of 3.3 V or 5 V and communications applications. The digital interface consists of two consumes 380 mW of power. double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent PRODUCT HIGHLIGHTS of one another. Separate clocks control the update rate of the DACs. 1. The AD9709 is a member of a pin-compatible family of A mode control pin allows the AD9709 to interface to two separate dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution. data ports, or to a single interleaved high speed data port. In inter- 2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance leaving mode, the input data stream is demuxed into its original DACs optimized for low distortion performance provide I and Q data and then latched. The I and Q data is then converted for flexible transmission of I and Q information. by the two DACs and updated at half the input data rate. 3. Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. The GAINCTRL pin allows two modes for setting the full-scale 4. Low Power. Complete CMOS dual DAC function operates current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set at 380 mW from a 3.3 V or 5 V single supply. The DAC independently using two external resistors, or IOUTFS for both full-scale current can be reduced for lower power operation, DACs can be set by using a single external resistor. See the Gain and a sleep mode is provided for low power idle periods. Control Mode section for important date code information on 5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V this feature. temperature-compensated band gap voltage reference. The DACs utilize a segmented current source architecture 6. Dual 8-Bit Inputs. The AD9709 features a flexible dual- combined with a proprietary switching technique to reduce port interface, allowing dual or interleaved input data. 1 Patent pending. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20002009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00606-001AD9709 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Outputs .......................................................................... 14 Applications ....................................................................................... 1 Digital Inputs .............................................................................. 15 Functional Block Diagram .............................................................. 1 DAC Timing ................................................................................ 15 General Description ......................................................................... 1 Sleep Mode Operation ............................................................... 18 Product Highlights ........................................................................... 1 Power Dissipation....................................................................... 18 Revision History ............................................................................... 2 Applying the AD9709 .................................................................... 19 Specif icat ions ..................................................................................... 3 Output Configurations .............................................................. 19 DC Specifications ......................................................................... 3 Differential Coupling Using a Transformer ............................ 19 Dynamic Specifications ............................................................... 4 Differential Coupling Using an Op Amp ................................ 19 Digital Specifications ................................................................... 5 Single-Ended, Unbuffered Voltage Output ............................. 20 Absolute Maximum Ratings ............................................................ 6 Single-Ended, Buffered Voltage Output Configuration ........ 20 Thermal Resistance ...................................................................... 6 Power and Grounding Considerations .................................... 20 ESD Caution .................................................................................. 6 Applications Information .............................................................. 22 Pin Configuration and Function Descriptions ............................. 7 Quadrature Amplitude Modulation (QAM) Using the AD9709 ........................................................................................ 22 Typical Performance Characteristics ............................................. 8 CDMA ......................................................................................... 23 Terminology .................................................................................... 11 Evaluation Board ............................................................................ 24 Theory of Operation ...................................................................... 12 General Description ................................................................... 24 Functional Description .............................................................. 12 Schematics ................................................................................... 24 Reference Operation .................................................................. 13 Evaluation Board Layout ........................................................... 30 Gain Control Mode .................................................................... 13 Outline Dimensions ....................................................................... 32 Setting the Full-Scale Current ................................................... 13 Ordering Guide .......................................................................... 32 DAC Transfer Function ............................................................. 14 REVISION HISTORY 9/09Rev. A to Rev. B Replaced Reference Control Amplifier Section with Setting Changes to Power and Grounding Considerations Section ..... 20 the Full-Scale Current Section ...................................................... 13 Changes to Schematics Section ..................................................... 24 Changes to DAC Transfer Function Section............................... 14 Changes to Evaluation Board Layout Section ............................. 30 Changes to Interleaved Mode Timing Section ........................... 16 Added Figure 28 ............................................................................. 16 1/08Rev. 0 to Rev. A Changes to Power and Grounding Considerations Section ..... 20 Updated Format .................................................................. Universal Changes to Figure 44 ...................................................................... 22 Changed Single Supply Operation to 5 V or 3.3 V ........ Universal Deleted Figure 43 ............................................................................ 17 Changes to Figure 1 .......................................................................... 1 Changes to CDMA Section ........................................................... 23 Added Timing Diagram Section .................................................... 5 Changes to Figure 45 Caption ...................................................... 23 Changes to Figure 3 and Table 6 ..................................................... 7 Changes to Figure 46 ...................................................................... 24 Change to Figure 12 ......................................................................... 9 Changes to Figure 48 ...................................................................... 26 Changes to Figure 18 to Figure 20 ................................................ 10 Updated Outline Dimensions ....................................................... 30 Changes to Functional Description Section ............................... 13 Changes to Ordering Guide .......................................................... 30 Changes to Reference Operation Section .................................... 13 Changes to Figure 23 and Figure 24 ............................................. 13 5/00Revision 0: Initial Version Changes to Gain Control Mode Section ...................................... 13 Rev. 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