16-Bit, 400 MSPS Digital-to-Analog Converter AD9726 FEATURES FUNCTIONAL BLOCK DIAGRAM Dynamic performance CLK+ SFDR 78 dBc at f = 20 MHz CLOCK DISTRIBUTION CSB OUT AND CONTROL CLK IMD 82 dBc at f = 70 MHz OUT SCLK ACLR 76 dBc at f = 70 MHz OUT SPI SDIO NSD 160 dB/Hz at f = 70 MHz OUT SDO DCLK OUT+ Precision calibrated linearity LVDS OUTPUT DRIVER RESET DCLK OUT DNL 0.5 LSB at +25C INL 1.0 LSB at +25C THD 95 dB at f = 1 MHz OUT CALIBRATION LVDS inputs with internal 100 terminations MEMORY DB 15 + Automatic data/clock timing synchronization Single data rate or double data rate capable DB 15 Differential current outputs IOUTA Internal precision reference 16-BIT DAC Operates on 2.5 V and 3.3 V supplies DB 0 + IOUTB Extended industrial temperature range DB 0 Thermally enhanced, 80-lead, RoHS-compliant TQFP EP package REFIO DCLK IN+ INTERNAL REFERENCE DCLK IN FSADJ APPLICATIONS Instrumentation Figure 1. Test equipment . Waveform synthesis Communications systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9726 is a 16-bit digital-to-analog converter (DAC) 1. A unique combination of precision and performance that offers leading edge performance at conversion rates of up makes the AD9726 equally suited to applications with to 400 MSPS. The device uses low voltage differential signaling demanding frequency domain or demanding time domain (LVDS) inputs and includes internal 100 terminations. The requirements. analog output can be single-ended or differential current. An 2. Nonvolatile factory calibration assures a highly linear internal precision reference is included. transfer function. Internal logic offers on demand self- calibration for linearity even at extended operating The AD9726 also features synchronization logic to monitor and temperatures. optimize the timing between incoming data and the sample clock. 3. Proprietary architecture minimizes data dependent, This reduces system complexity and simplifies timing require- discrete mixing spurs and offers enhanced dynamic ments. An LVDS clock output is also available to drive an external performance over a wide range of output frequencies. data pump in either single data rate (SDR) or double data rate High input data rates create a very high frequency (DDR) mode. synthesis bandwidth. All device operation is fully programmable using the flexible 4. The fully automatic, transparent synchronizer maintains serial port interface (SPI). The AD9726 is also fully functional optimized timing between clock and data in real time and in its default state for applications without a controller. offers programmable control options for added flexibility. 5. Full-scale output current is external resistor programmable. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. LVDS INPUT DATA CAPTURE DATA SYNCHRONIZATION 04540-001AD9726 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 12 Applications ....................................................................................... 1 Serial Port Interface ........................................................................ 15 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 17 General Description ......................................................................... 1 DAC Clock and Data Clock Output ........................................ 17 Product Highlights ........................................................................... 1 Data Clock Input ........................................................................ 17 Revision History ............................................................................... 2 Data Synchronization Circuitry ............................................... 18 Specif icat ions ..................................................................................... 3 Analog Output ............................................................................ 18 DC Specifications ......................................................................... 3 Internal Reference and Full-Scale Output .............................. 19 AC Specifications .......................................................................... 4 Reset ............................................................................................. 19 Digital Signal Specifications ........................................................ 5 Serial Port Interface ................................................................... 19 Timing Specifications .................................................................. 5 SPI Pin Description .................................................................... 20 Timing Diagrams .......................................................................... 6 C a l ibr at ion ................................................................................... 20 Absolute Maximum Ratings ............................................................ 8 Sync Logic Operation and Programming ............................... 22 Thermal Resistance ...................................................................... 8 Outline Dimensions ....................................................................... 24 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 24 Pin Configuration and Function Descriptions ............................. 9 Terminology .................................................................................... 11 REVISION HISTORY 2/10Rev. A to Rev. B 11/05Rev. 0 to Rev. A Changes to Table 4 ............................................................................ 5 Changes to Features .......................................................................... 1 Added Figure 4 and Figure 5, Renumbered Sequentially ........... 6 Changes to Table 3 and Table 4 ....................................................... 5 Changes to Figure 5 and Table 7 ..................................................... 9 Changes to the Terminology Section ........................................... 10 Changes to Table 9 .......................................................................... 16 Changes to the Driving the DAC Clock Inputs Section ............ 15 Added Data Synchronization Circuitry Bypass Section ............ 18 Changes to the Reset and Serial Port Interface Sections ........... 17 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 22 Changes to the Ordering Guide ................................................... 22 7/05Revision 0: Initial Version Rev. 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