10-/12-/14-Bit, 1200 MSPS DACS Data Sheet AD9734/AD9735/AD9736 FEATURES FUNCTIONAL BLOCK DIAGRAM DACCLK DACCLK+ RESET IRQ Pin-compatible family S1S2S3 Excellent dynamic performance AD9736: SFDR = 82 dBc at f = 30 MHz SDIO OUT C1 SDO AD9736: SFDR = 69 dBc at f = 130 MHz SPI CONTROLLER C2 OUT CSB C3 AD9736: IMD = 87 dBc at f = 30 MHz SCLK C3 OUT AD9736: IMD = 82 dBc at f = 130 MHz OUT DATACLK OUT+ CLOCK DISTRIBUTION DATACLK OUT LVDS data interface with on-chip 100 terminations S3 Built-in self test LVDS sampling integrity IOUTA 2 14-, 12-, DATACLK IN+ 10-BIT DAC DATACLK IN LVDS-to-DAC data transfer integrity CORE IOUTB DB 13:0 + Low power: 380 mW (I = 20 mA f = 330 MHz) FS OUT DB 13:0 1.8/3.3 V dual-supply operation REFERENCE BAND GAP Adjustable analog output C2 CURRENT S2 C1S1 8.66 mA to 31.66 mA (R = 25 to 50 ) L On-chip 1.2 V reference VREF I120 160-lead chip scale ball grid array (CSP BGA) package Figure 1. APPLICATIONS PRODUCT HIGHLIGHTS Broadband communications systems Cellular infrastructure (digital predistortion) 1. Low noise and intermodulation distortion (IMD) features Point-to-point wireless enable high quality synthesis of wideband signals at inter- CMTS/VOD mediate frequencies up to 600 MHz. Instrumentation, automatic test equipment 2. Double data rate (DDR) LVDS data receivers support the Radar, avionics maximum conversion rate of 1200 MSPS. 3. Direct pin programmability of basic functions or SPI port GENERAL DESCRIPTION access offers complete control of all AD973x family The AD9736, AD9735, and AD9734 are high performance, high functions. frequency DACs that provide sample rates of up to 1200 MSPS, 4. Manufactured on a CMOS process, the AD973x family permitting multicarrier generation up to their Nyquist uses a proprietary switching technique that enhances frequency. The AD9736 is the 14-bit member of the family, dynamic performance. while the AD9735 and the AD9734 are the 12-bit and 10-bit 5. The current output(s) of the AD9736 family are easily con- members, respectively. They include a serial peripheral interface figured for single-ended or differential circuit topologies. (SPI) port that provides for programming of many internal parameters and enables readback of status registers. A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is manufactured on a 0.18 m CMOS process and operates from 1.8 V and 3.3 V supplies for a total power consumption of 380 mW in bypass mode. It is supplied in a 160-lead chip scale ball grid array for reduced package parasitics. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com LVDS LVDS RECEIVER DRIVER SYNCHRONIZER 04862-001AD9734/AD9735/AD9736 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Built-In Self Test Control (BIST CNT) Registers (Reg. 17, Reg. 18, Reg. 19, Reg. 20, Reg. 21) ........................................... 33 Applications ....................................................................................... 1 Controller Clock Predivider (CCLK DIV) Reading Register General Description ......................................................................... 1 (Reg. 22) ....................................................................................... 34 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 35 Product Highlights ........................................................................... 1 Serial Peripheral Interface ............................................................. 36 Revision History ............................................................................... 3 General Operation of the Serial Interface ............................... 36 Specifications ..................................................................................... 4 Short Instruction Mode (8-Bit Instruction) ........................... 36 DC Specifications ......................................................................... 4 Long Instruction Mode (16-Bit Instruction) .......................... 36 Digital Specifications ................................................................... 6 Serial Interface Port Pin Descriptions ..................................... 36 AC Specifications .......................................................................... 8 SCLKSerial Clock ............................................................... 36 Absolute Maximum Ratings ............................................................ 9 CSBChip Select ................................................................... 37 Thermal Resistance ...................................................................... 9 SDIOSerial Data I/O .......................................................... 37 Pin Configurations and Function Descriptions ......................... 10 SDOSerial Data Out .......................................................... 37 Location of Supply and Control Pins ....................................... 16 MSB/LSB Transfers .................................................................... 37 Terminology .................................................................................... 17 Notes on Serial Port Operation ................................................ 37 Typical Performance Characteristics ........................................... 18 Pin Mode Operation .................................................................. 38 AD9736 Static Linearity, 10 mA Full Scale ............................. 18 RESET Operation ....................................................................... 38 AD9736 Static Linearity, 20 mA Full Scale ............................. 19 Programming Sequence ............................................................ 38 AD9736 Static Linearity, 30 mA Full Scale ............................. 20 Interpolation Filter ..................................................................... 39 AD9735 Static Linearity, 10 mA, 20 mA, 30 mA Data Interface Controllers ......................................................... 39 Full Scale ...................................................................................... 21 LVDS Sample Logic .................................................................... 40 AD9734 Static Linearity, 10 mA, 20 mA, 30 mA Full Scale ...................................................................................... 22 LVDS Sample Logic Calibration ............................................... 40 AD9736 Power Consumption, 20 mA Full Scale ....................... 23 Operating the LVDS Controller in Manual Mode via the SPI Port ........................................................................................ 41 AD9736 Dynamic Performance, 20 mA Full Scale................ 24 Operating the LVDS Controller in Surveillance and Auto AD9735, AD9734 Dynamic Performance, 20 mA Mode ............................................................................................ 41 Full Scale ...................................................................................... 27 SYNC Logic and Controller .......................................................... 42 AD973x WCDMA ACLR, 20 mA Full Scale .......................... 28 SYNC Logic and Controller Operation ................................... 42 SPI Register Map ............................................................................. 29 Operation in Manual Mode ...................................................... 42 SPI Register Details ........................................................................ 30 Operation in Surveillance and Auto Modes ........................... 42 Mode Register (Reg. 0) .............................................................. 30 FIFO Bypass ................................................................................ 42 Interrupt Request Register (IRQ) (Reg. 1) .............................. 30 Digital Built-In Self Test (BIST) ................................................... 44 Full Scale Current (FSC) Registers (Reg. 2, Reg. 3) ............... 31 Overview ..................................................................................... 44 LVDS Controller (LVDS CNT) Registers (Reg. 4, Reg. 5, Reg. 6) .......................................................................................... 31 AD973x BIST Procedure ........................................................... 45 SYNC Controller (SYNC CNT) Registers (Reg. 7, AD973x Expected BIST Signatures.......................................... 45 Reg. 8) .......................................................................................... 32 Generating Expected Signatures .............................................. 46 Cross Controller (CROS CNT) Registers (Reg. 10, Cross Controller Registers............................................................. 47 Reg. 11) ........................................................................................ 32 Analog Control Registers .............................................................. 48 Analog Control (ANA CNT) Registers (Reg. 14, Band Gap Temperature Characteristic Trim Bits................... 48 Reg. 15) ........................................................................................ 33 Mirror Roll-Off Frequency Control ........................................ 48 Rev. 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