Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters Data Sheet AD9741 FEATURES GENERAL DESCRIPTION High dynamic range, dual DACs The AD9741/AD9743/AD9745/AD9746/AD9747 are pin- Low noise and intermodulation distortion compatible, high dynamic range, dual digital-to-analog Single carrier WCDMA ACLR = 80 dBc at 61.44 MHz IF converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions Innovative switching output stage permits useable outputs and sample rates of up to 250 MSPS. The devices include beyond Nyquist frequency specific features for direct conversion transmit applications, LVCMOS inputs with dual-port or optional interleaved including gain and offset compensation, and they interface single-port operation seamlessly with analog quadrature modulators, such as the Differential analog current outputs are programmable from ADL5370. 8.6 mA to 31.7 mA full scale A proprietary, dynamic output architecture permits synthesis Auxiliary 10-bit current DACs with source/sink capability for of analog outputs even above Nyquist by shifting energy away external offset nulling from the fundamental and into the image frequency. Internal 1.2 V precision reference voltage source Full programmability is provided through a serial peripheral Operates from 1.8 V and 3.3 V supplies interface (SPI) port. In addition, some pin-programmable 315 mW power dissipation features are offered for those applications without a controller. Small footprint, Pb-free, 72-pin LFCSP PRODUCT HIGHLIGHTS APPLICATIONS 1. Low noise and intermodulation distortion (IMD) enables Wireless infrastructure: high quality synthesis of wideband signals. WCDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications: 2. Proprietary switching output for enhanced dynamic LMDS/MMDS, point-to-point performance. Instrumentation: 3. Programmable current outputs and dual auxiliary DACs RF signal generators, arbitrary waveform generators provide flexibility and system enhancements. FUNCTIONAL BLOCK DIAGRAM CLKP CLKN IOUT1P 16-BIT DAC1 IOUT1N INTERFACE LOGIC IOUT2P 16-BIT PID<15:0> DAC2 IOUT2N GAIN 10 DAC CMOS INTERFACE GAIN DAC AUX1P P2D<15:0> INTERNAL OFFSET DAC REFERENCE AUX1N AND SERIAL AUX2P BIAS OFFSET PERIPHERAL DAC AUX2N INTERFACE Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com OBSOLETE SDO SDIO SCLK CSB REFIO FSADJ 06569-001AD9741 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Instruction Byte .......................................................................... 18 Applications ....................................................................................... 1 MSB/LSB Transfers .................................................................... 19 General Description ......................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 19 Product Highlights ........................................................................... 1 SPI Register Map ............................................................................ 20 Functional Block Diagram .............................................................. 1 SPI Register Descriptions .............................................................. 21 Revision History ............................................................................... 2 Digital Inputs and Outputs ........................................................... 22 Specifications ..................................................................................... 3 Input Data Timing ..................................................................... 22 DC Specifications ......................................................................... 3 Dual-Port Mode Timing ........................................................... 22 AC Specifications .......................................................................... 5 Single-Port Mode Timing ......................................................... 22 Digital and Timing Specifications .............................................. 7 SPI Port, Reset, and Pin Mode .................................................. 22 Absolute Maximum Ratings ............................................................ 8 Driving the DAC Clock Input .................................................. 23 Thermal Resistance ...................................................................... 8 Full-Scale Current Generation ................................................. 23 ESD Caution .................................................................................. 8 DAC Transfer Function ............................................................. 24 Pin Configurations and Function Descriptions ........................... 9 Analog Modes of Operation ..................................................... 24 Typical Performance Characteristics ........................................... 14 Auxiliary DACS .......................................................................... 25 Terminology .................................................................................... 17 Power Dissipation....................................................................... 25 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 27 Serial Peripheral Interface ......................................................... 18 Ordering Guide .......................................................................... 27 General Operation of the Serial Interface ............................... 18 REVISION HISTORY 1/14Rev. 0 to Rev. A Changes to Table 15 ........................................................................ 21 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 5/07Revision 0: Initial Version Rev. B Page 2 of 28 OBSOLETE