12-Bit, 210 MSPS TxDAC Digital-to-Analog Converter Data Sheet AD9742 FEATURES FUNCTIONAL BLOCK DIAGRAM 3.3V High performance member of pin-compatible TxDAC product family REFLO AVDD ACOM 150pF Excellent spurious-free dynamic range performance 1.2V REF 0.1F SNR at 5 MHz output, 125 MSPS: 70 dB AD9742 REFIO CURRENT SOURCE Twos complement or straight binary data format FS ADJ ARRAY Differential current outputs: 2 mA to 20 mA R SET 3.3V DVDD IOUTA SEGMENTED LSB Power dissipation: 135 mW at 3.3 V DCOM IOUTB SWITCHES SWITCHES Power-down mode: 15 mW at 3.3 V CLOCK CLOCK LATCHES MODE On-chip 1.2 V Reference CMOS compatible digital interface DIGITAL DATA INPUTS (DB11DB0) 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP SLEEP Edge-triggered latches Figure 1. APPLICATIONS Wideband communication transmit channel: Direct IF Base stations Wireless local loops Digital radio links Direct digital synthesis (DDS) Instrumentation GENERAL DESCRIPTION 1 The AD9742 is a 12-bit resolution, wideband, third generation Edge-triggered input latches and a 1.2 V temperature compensated member of the TxDAC series of high performance, low power band gap reference have been integrated to provide a complete CMOS digital-to-analog converters (DACs). The TxDAC family, monolithic DAC solution. The digital inputs support 3 V CMOS consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, logic families. is specifically optimized for the transmit signal path of PRODUCT HIGHLIGHTS communication systems. All of the devices share the same interface 1. The AD9742 is the 12-bit member of the pin-compatible options, small outline package, and pinout, providing an upward TxDAC family, which offers excellent INL and DNL or downward component selection path based on performance, performance. resolution, and cost. The AD9742 offers exceptional ac and dc 2. Data input supports twos complement or straight binary performance while supporting update rates up to 210 MSPS. data coding. The AD9742s low power dissipation makes it well suited for 3. High speed, single-ended CMOS clock input supports portable and low power applications. Its power dissipation can 210 MSPS conversion rate. be further reduced to a mere 60 mW with a slight degradation 4. Low power: Complete CMOS DAC function operates on in performance by lowering the full-scale current output. Also, 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- a power-down mode reduces the standby power dissipation to scale current can be reduced for lower power operation, approximately 15 mW. A segmented current source architecture and a sleep mode is provided for low power idle periods. is combined with a proprietary switching technique to reduce 5. On-chip voltage reference: The AD9742 includes a 1.2 V spurious components and enhance dynamic performance. temperature compensated band gap voltage reference. 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages. 1 Protected by U.S. Patent Numbers: 5,568,145 5,689,257 and 5,703,519. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 02913-B-001AD9742 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference Control Amplifier .................................................... 13 Applications ....................................................................................... 1 DAC Transfer Function ............................................................. 13 Functional Block Diagram .............................................................. 1 Analog Outputs .......................................................................... 13 General Description ......................................................................... 1 Digital Inputs .............................................................................. 14 Product Highlights ........................................................................... 1 Clock Input.................................................................................. 14 Revision History ............................................................................... 2 DAC Timing ................................................................................ 15 Specifications ..................................................................................... 3 Power Dissipation....................................................................... 15 DC Specifications ......................................................................... 3 Applying the AD9742 ................................................................ 16 Dynamic Specifications ............................................................... 4 Differential Coupling Using a Transformer ............................... 16 Digital Specifications ................................................................... 5 Differential Coupling Using an Op Amp ................................ 16 Absolute Maximum Ratings ............................................................ 6 Single-Ended, Unbuffered Voltage Output ............................. 17 Thermal Resistance ...................................................................... 6 Single-Ended, Buffered Voltage Output Configuration ........ 17 ESD Caution .................................................................................. 6 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 17 Pin Configurations and Function Descriptions ........................... 7 Evaluation Board ............................................................................ 19 Typical Performance Characteristics ............................................. 8 General Description ................................................................... 19 Terminology .................................................................................... 11 Outline Dimensions ....................................................................... 29 Functional Description .................................................................. 12 Ordering Guide .......................................................................... 30 Reference Operation .................................................................. 12 REVISION HISTORY 2/13Rev. B to Rev. C 5/03Rev. 0 to Rev. A Updated Format .................................................................. Universal Added 32-Lead LFCSP Package ....................................... Universal Changes to Figure 4 and Table 6 ..................................................... 7 Edits to Features and Product Highlights ...................................... 1 Moved Terminology Section ......................................................... 11 Edits to DC Specifications ................................................................ 2 Updated Outline Dimensions ....................................................... 29 Edits to Dynamic Specifications ...................................................... 3 Changes to Ordering Guide .......................................................... 30 Edits to Digital Specifications .......................................................... 4 Edits to Absolute Maximum Ratings, Thermal Characteristics, 6/04Rev. A to Rev. B and Ordering Guide .......................................................................... 5 Changes to the Title, General Description, and Product Edits to Pin Configuration and Pin Function Descriptions ........ 6 Highlights .......................................................................................... 1 Edits to Figure 2 ................................................................................. 7 Changes to Dynamic Specifications ............................................... 4 Replaced TPCs 1, 4, 7, and 8 ............................................................ 8 Changes to Figure 6 and Figure 10 ................................................. 9 Edits to Figure 3 and Functional Description Section .............. 10 Changes to Figure 12 to Figure 15 ................................................ 10 Added Clock Input Section and Figure 7 .................................... 12 Changes to the Functional Description Section ......................... 12 Edits to DAC Timing Section ....................................................... 12 Edits to Sleep Mode Operation Section and Power Dissipation Changes to the Digital Inputs Section ......................................... 14 Changes to Figure 29 ...................................................................... 15 Section .............................................................................................. 13 Changes to Figure 30 ...................................................................... 16 Renumbered Figure 8 to Figure 26............................................... 13 Added Figure 11 ............................................................................. 13 Added Figure 27 to Figure 35 ....................................................... 21 Updated Outline Dimensions ....................................................... 26 5/02Revision 0: Initial Version Rev. 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