Dual, 10-/12-/14-/16-Bit, 250 MSPS, Digital-to-Analog Converters Data Sheet AD9743/AD9745/AD9746/AD9747 FEATURES GENERAL DESCRIPTION High dynamic range, dual digital-to-analog converters (DACs) The AD9743/AD9745/AD9746/AD9747 are pin-compatible, Low noise and intermodulation distortion high dynamic range, dual DACs with 10-/12-/ 14-/16-bit Single carrier W-CDMA ACLR = 80 dBc at 61.44 MHz resolutions and sample rates of up to 250 MSPS. The devices intermediate frequency (IF) include specific features for direct conversion transmit applications, Innovative switching output stage permits useable outputs including gain and offset compensation, and they interface beyond Nyquist frequency seamlessly with analog quadrature modulators, such as the LVCMOS inputs with dual-port or optional interleaved ADL5370. single-port operation A proprietary, dynamic output architecture permits synthesis of Differential analog current outputs are programmable from analog outputs even above Nyquist by shifting energy away from 8.6 mA to 31.7 mA full-scale the fundamental and into the image frequency. Auxiliary 10-bit current DACs with source/sink capability for A serial peripheral interface (SPI) port provides full external offset nulling programmability. In addition, some pin-programmable features Internal 1.2 V precision reference voltage source are offered for those applications without a controller. Operates from 1.8 V and 3.3 V supplies 315 mW power dissipation PRODUCT HIGHLIGHTS Small footprint, RoHS-compliant, 72-lead LFCSP 1. Low noise and intermodulation distortion (IMD) enables APPLICATIONS high quality synthesis of wideband signals. 2. Proprietary switching output for enhanced dynamic Wireless infrastructure performance. W-CDMA, CDMA2000, TD-SCDMA, WiMAX 3. Programmable current outputs and dual auxiliary DACs Wideband communications: LMDS/MMDS, point-to-point provide flexibility and system enhancements. Instrumentation Radio frequency (RF) signal generators, arbitrary waveform generators FUNCTIONAL BLOCK DIAGRAM CLKP CLKN IOUT1P 16-BIT DAC1 IOUT1N INTERFACE LOGIC IOUT2P 16-BIT PID<15:0> DAC2 IOUT2N GAIN 10 DAC CMOS INTERFACE GAIN DAC AUX1P P2D<15:0> INTERNAL OFFSET DAC REFERENCE AUX1N AND SERIAL AUX2P BIAS OFFSET PERIPHERAL DAC AUX2N INTERFACE Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SDO SDIO SCLK CSB REFIO FSADJ 06569-001AD9743/AD9745/AD9746/AD9747 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Instruction Byte .......................................................................... 21 Applications ....................................................................................... 1 MSB/LSB Transfers .................................................................... 22 General Description ......................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 22 Product Highlights ........................................................................... 1 SPI Register Map ............................................................................ 23 Functional Block Diagram .............................................................. 1 SPI Register Descriptions .............................................................. 24 Revision History ............................................................................... 2 Digital Inputs and Outputs ........................................................... 25 Specif icat ions ..................................................................................... 3 Input Data Timing ..................................................................... 25 DC Specifications ......................................................................... 3 Dual-Port Mode Timing ........................................................... 25 AC Specifications .......................................................................... 5 Single-Port Mode Timing ......................................................... 25 Digital and Timing Specifications .............................................. 7 SPI Port, Reset, and Pin Mode .................................................. 25 Absolute Maximum Ratings ............................................................ 8 Driving the DAC Clock Input .................................................. 26 Thermal Resistance ...................................................................... 8 Full-Scale Current Generation ................................................. 26 ESD Caution .................................................................................. 8 DAC Transfer Function ............................................................. 27 Pin Configurations and Function Descriptions ........................... 9 Analog Modes of Operation ..................................................... 27 Typical Performance Characteristics ........................................... 17 Auxiliary DACS .......................................................................... 28 Terminology .................................................................................... 20 Power Dissipation....................................................................... 28 Theory of Operation ...................................................................... 21 Outline Dimensions ....................................................................... 30 SPI PORT ..................................................................................... 21 Ordering Guide .......................................................................... 30 General Operation of the Serial Interface ............................... 21 REVISION HISTORY 9/15Rev. A to Rev. B Changes to Figure 19 and Figure 20............................................. 19 Deleted AD9741.................................................................. Universal Changes to Figure 39 and Figure 40............................................. 28 Changed NC to DNC .................................................... Throughout Changes to Ordering Guide .......................................................... 31 Deleted Figure 2 Renumbered Sequentially and Table 8 Renumbered Sequentially ................................................................ 9 1/14Rev. 0 to Rev. A Changes to Figure 2 .......................................................................... 9 Changes to Table 15 ....................................................................... 21 Changes to Figure 3 ........................................................................ 11 Updated Outline Dimensions ....................................................... 27 Changes to Figure 4 ........................................................................ 13 Changes to Ordering Guide .......................................................... 27 Changes to Figure 5 ........................................................................ 15 Changes to Figure 12 Caption, Figure 13 Caption, Figure 15 5/07Revision 0: Initial Version Caption, and Figure 16 Caption ................................................... 18 Rev. B Page 2 of 30