8-Bit, 210 MSPS TxDAC D/A Converter Data Sheet AD9748 FEATURES APPLICATIONS High performance member of pin-compatible Communications TxDAC product family Direct digital synthesis (DSS) Linearity Instrumentation 0.1 LSB DNL FUNCTIONAL BLOCK DIAGRAM 0.1 LSB INL 3.3V Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA AVDD ACOM 150pF Power dissipation: 135 mW 3.3 V 1.2V REF 0.1 F AD9748 Power-down mode: 15 mW 3.3 V REFIO CURRENT SOURCE FS ADJ On-chip 1.20 V reference ARRAY R SET CMOS-compatible digital interface 3.3V DVDD IOUTA SEGMENTED LSB DCOM IOUTB 32-lead LFCSP SWITCHES SWITCHES Edge-triggered latches CLK+ MODE LATCHES CMODE Fast settling: 11 ns to 0.1% full-scale CLK 3.3V CLKVDD CLKCOM DIGITAL DATA INPUTS (DB7DB0) SLEEP Figure 1. GENERAL DESCRIPTION 1 Edge-triggered input latches and a 1.2 V temperature- The AD9748 is an 8-bit resolution, wideband, third generation compensated band gap reference have been integrated to member of the TxDAC series of high performance, low power provide a complete monolithic DAC solution. The digital inputs CMOS digital-to-analog converters (DACs). The TxDAC support 3 V CMOS logic families. family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same PRODUCT HIGHLIGHTS interface options, small outline package, and pinout, providing an upward or downward component selection path based on 1. 32-lead LFCSP. performance, resolution, and cost. The AD9748 offers 2. The AD9748 is the 8-bit member of the pin-compatible exceptional ac and dc performance while supporting update TxDAC family, which offers excellent INL and DNL rates up to 210 MSPS. performance. 3. Differential or single-ended clock input (LVPECL or The AD9748s low power dissipation makes it well suited for CMOS), supports 210 MSPS conversion rate. portable and low power applications. Its power dissipation can 4. Data input supports twos complement or straight binary be further reduced to 60 mW with a slight degradation in data coding. performance by lowering the full-scale current output. In 5. Low power: Complete CMOS DAC function operates on addition, a power-down mode reduces the standby power 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- dissipation to approximately 15 mW. A segmented current scale current can be reduced for lower power operation, source architecture is combined with a proprietary switching and a sleep mode is provided for low power idle periods. technique to reduce spurious components and enhance 6. On-chip voltage reference: The AD9748 includes a 1.2 V dynamic performance. temperature-compensated band gap voltage reference. 1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03211-001AD9748 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference Control Amplifier .................................................... 11 Applications ....................................................................................... 1 DAC Transfer Function ............................................................. 12 Functional Block Diagram .............................................................. 1 Analog Outputs .......................................................................... 12 General Description ......................................................................... 1 Digital Inputs .............................................................................. 13 Product Highlights ........................................................................... 1 Clock Input .................................................................................. 13 Revision History ............................................................................... 2 DAC Timing ................................................................................ 14 Specifications ..................................................................................... 3 Power Dissipation....................................................................... 14 DC Specifications ......................................................................... 3 Applying the AD9748 ................................................................ 15 Dynamic Specifications ............................................................... 4 Differential Coupling Using a Transformer ............................... 15 Digital Specifications ................................................................... 5 Differential Coupling Using an Op Amp ................................ 16 Absolute Maximum Ratings ............................................................ 6 Single-Ended, Unbuffered Voltage Output ............................. 16 Thermal Characteristics .............................................................. 6 Single-Ended, Buffered Voltage Output Configuration ........ 16 ESD Caution .................................................................................. 6 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 17 Pin Configuration and Function Descriptions ............................. 7 Evaluation Board ............................................................................ 18 Terminology ...................................................................................... 8 General Description ................................................................... 18 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 24 Functional Description .................................................................. 11 Ordering Guide .......................................................................... 24 Reference Operation .................................................................. 11 REVISION HISTORY Changes to Functional Description, Reference Operation, and 3/13Rev. A to Rev. B Reference Control Amplifier Sections ......................................... 11 Changed CP-32-2 to CP-32-7 ........................................... Universal Inserted Figure 16 Renumbered Sequentially ........................... 11 Changes to Figure 3 and Table 5 ..................................................... 7 Changes to DAC Transfer Function Section............................... 12 Changes to Ordering Guide .......................................................... 24 Changes to Digital Inputs Section ................................................ 13 12/05Rev. 0 to Rev. A Changes to Figure 22, Figure 23, and Figure 24 ......................... 14 Updated Format .................................................................. Universal Changes to Figure 25 ...................................................................... 15 Changes to General Description and Product Highlights .......... 1 Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16 Changes to Table 1 ............................................................................ 3 Updated Outline Dimensions ....................................................... 24 Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide .......................................................... 24 Changes to Table 4 ............................................................................ 6 2/03Revision 0: Initial Version Inserted Figure 7 Renumbered Sequentially ................................ 9 Changes to Figure 8 and Figure 9 ................................................... 9 Rev. B Page 2 of 24