10-Bit, 125 MSPS High Performance a TxDAC D/A Converter AD9750 FUNCTIONAL BLOCK DIAGRAM FEATURES High Performance Member of Pin-Compatible +5V TxDAC Product Family REFLO AVDD ACOM 125 MSPS Update Rate 150pF +1.20V REF AD9750 10-Bit Resolution 0.1mF REFIO 0.1mF CURRENT ICOMP Excellent Spurious Free Dynamic Range Performance FS ADJ SOURCE ARRAY SFDR to Nyquist 5 MHz Output: 76 dBc R SET DVDD +5V IOUTA Differential Current Outputs: 2 mA to 20 mA SEGMENTED LSB DCOM IOUTB SWITCHES SWITCH Power Dissipation: 190 mW 5 V CLOCK Power-Down Mode: 20 mW 5 V CLOCK LATCHES SLEEP On-Chip 1.20 V Reference CMOS-Compatible +2.7 V to +5.5 V Digital Interface DIGITAL DATA INPUTS (DB9DB0) Packages: 28-Lead SOIC and TSSOP The AD9750 is a current-output DAC with a nominal full-scale Edge-Triggered Latches output current of 20 mA and > 100 kW output impedance. APPLICATIONS Differential current outputs are provided to support single- Wideband Communication Transmit Channel: ended or differential applications. Matching between the two Direct IF current outputs ensures enhanced dynamic performance in a Basestations differential output configuration. The current outputs may be Wireless Local Loop tied directly to an output resistor to provide two complemen- Digital Radio Link tary, single-ended voltage outputs or fed directly into a trans- Direct Digital Synthesis (DDS) former. The output voltage compliance range is 1.25 V. Instrumentation The on-chip reference and control amplifier are configured for PRODUCT DESCRIPTION maximum accuracy and flexibility. The AD9750 can be driven The AD9750 is a 10-bit resolution, wideband, second generation by the on-chip reference or by a variety of external reference member of the TxDAC series of high performance, low power voltages. The internal control amplifier, which provides a wide CMOS digital-to-analog-converters (DACs). The TxDAC family, (>10:1) adjustment span, allows the AD9750 full-scale current which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, to be adjusted over a 2 mA to 20 mA range while maintaining is specifically optimized for the transmit signal path of commu- excellent dynamic performance. Thus, the AD9750 may oper- nication systems. All of the devices share the same interface ate at reduced power levels or be adjusted over a 20 dB range to options, small outline package and pinout, thus providing an up- provide additional gain ranging capabilities. ward or downward component selection path based on perfor- The AD9750 is available in 28-lead SOIC and TSSOP packages. mance, resolution and cost. The AD9750 offers exceptional ac and It is specified for operation over the industrial temperature range. dc performance while supporting update rates up to 125 MSPS. The AD9750s flexible single-supply operating range of 4.5 V to PRODUCT HIGHLIGHTS 5.5 V and low power dissipation are well suited for portable and 1. The AD9750 is a member of the wideband TxDAChigh per- low power applications. Its power dissipation can be further formance product family that provides an upward or downward reduced to a mere 65 mW, without a significant degradation in component selection path based on resolution (8 to 14 bits), performance, by lowering the full-scale current output. Also, a performance and cost. The entire family of TxDACs is avail- power-down mode reduces the standby power dissipation to able in industry standard pinouts. apprixmatley 20 mW. 2. Manufactured on a CMOS process, the AD9750 uses a The AD9750 is manufactured on an advanced CMOS process. proprietary switching technique that enhances dynamic A segmented current source architecture is combined with a performance beyond that previously attainable by higher proprietary switching technique to reduce spurious components power/cost bipolar or BiCMOS devices. and enhance dynamic performance. Edge-triggered input latches 3. On-chip, edge-triggered input CMOS latches interface to and a 1.2 V temperature compensated bandgap reference have +2.7 V to +5 V CMOS logic families. The AD9750 can been integrated to provide a complete monolithic DAC solution. support update rates up to 125 MSPS. The digital inputs support +2.7 V and +5 V CMOS logic families. 4. A flexible single-supply operating range of +4.5 V to +5.5 V, TxDAC is a registered trademark of Analog Devices, Inc. and a wide full-scale current adjustment span of 2 mA to *Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and 20 mA, allows the AD9750 to operate at reduced power levels. 5703519. 5. The current output(s) of the AD9750 can be easily config- REV. 0 ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD9750SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) DC SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 10 Bits 1 DC ACCURACY Integral Linearity Error (INL) 1.0 0.1 +1.0 LSB Differential Nonlinearity (DNL) 0.5 0.1 +0.5 LSB ANALOG OUTPUT Offset Error 0.02 +0.02 % of FSR Gain Error (Without Internal Reference) 2 0.5 +2 % of FSR Gain Error (With Internal Reference) 5 1.5 +5 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range 1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/ C Gain Drift (Without Internal Reference) 50 ppm of FSR/ C Gain Drift (With Internal Reference) 100 ppm of FSR/ C Reference Voltage Drift 50 ppm/ C POWER SUPPLY Supply Voltages AVDD 4.5 5.0 5.5 V DVDD 2.7 5.0 5.5 V 4 ) 33 39 mA Analog Supply Current (I AVDD 5 Digital Supply Current (I ) 5.0 7 mA DVDD 6 Supply Current Sleep Mode (I ) 4.0 8 mA AVDD 5 (5 V, I = 20 mA) 190 230 mW Power Dissipation OUTFS 7 Power Supply Rejection Ratio AVDD 0.4 +0.4 % of FSR/V 7 Power Supply Rejection Ratio DVDD 0.025 +0.025 % of FSR/V OPERATING RANGE 40 +85 C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Requires +5 V supply. 5 Measured at f = 50 MSPS and I = static full scale (20 mA). CLOCK OUT 6 Logic level for SLEEP pin must be referenced to AVDD. Min V = 3.5 V. IH 7 5% Power supply variation. Specifications subject to change without notice. 2 REV. 0