10-Bit, 300 MSPS a High Speed TxDAC+ D/A Converter * AD9751 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-Bit Dual Muxed Port DAC DVDD DCOM AVDD ACOM 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist 25 MHz Output: 64 dB LATCH PORT1 I OUTA Internal Clock Doubling PLL MUX DAC Differential or Single-Ended Clock Input I PORT2 LATCH OUTB On-Chip 1.2 V Reference Single 3.3 V Supply Operation CLK+ REFIO Power Dissipation: 155 mW 3.3 V PLL CLK REFERENCE FSADJ CLOCK CLKVDD 48-Lead LQFP MULTIPLIER PLLVDD CLKCOM AD9751 APPLICATIONS Communications: LMDS, LMCS, MMDS RESET LPF DIV0 DIV1 PLLLOCK Base Stations Digital Synthesis QAM and OFDM PRODUCT DESCRIPTION The DAC utilizes a segmented current source architecture com- The AD9751 is a dual muxed port, ultrahigh speed, single- bined with a proprietary switching technique to reduce glitch channel, 10-bit CMOS DAC. It integrates a high quality 10-bit energy and maximize dynamic accuracy. Differential current TxDAC+ core, a voltage reference, and digital interface circuitry outputs support single-ended or differential applications. The into a small 48-lead LQFP package. The AD9751 offers excep- differential outputs each provide a nominal full-scale current tional ac and dc performance while supporting update rates up from 2 mA to 20 mA. to 300 MSPS. The AD9751 is manufactured on an advanced low cost 0.35 m The AD9751 has been optimized for ultrahigh speed applica- CMOS process. It operates from a single supply of 3.0 V to 3.6 V tions up to 300 MSPS where data rates exceed those possible on and consumes 155 mW of power. a single data interface port DAC. The digital interface consists of two buffered latches as well as control logic. These latches PRODUCT HIGHLIGHTS can be time multiplexed to the high speed DAC in several ways. 1. The AD9751 is a member of a pin compatible family of high This PLL drives the DAC latch at twice the speed of the exter- speed TxDAC+s, providing 10-, 12-, and 14-bit resolution. nally applied clock and is able to interleave the data from the 2. Ultrahigh Speed 300 MSPS Conversion Rate. two input channels. The resulting output data rate is twice that 3. Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751 of the two input channels. With the PLL disabled, an external features a flexible digital interface allowing high speed data 2 clock may be supplied and divided by two internally. conversion through either a single or dual port input. The CLK inputs (CLK+/CLK) can be driven either differen- 4. Low Power. Complete CMOS DAC function operates on tially or single-ended, with a signal swing as low as 1 V p-p. 155 mW from a 3.0 V to 3.6 V single supply. The DAC full- scale current can be reduced for lower power operation. 5. On-Chip Voltage Reference. The AD9751 includes a 1.20 V temperature compensated band gap voltage reference. *Protected by U.S. Patent numbers 5450084, 5568145, 5689257, and 5703519. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. DAC LATCHAD9751* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS View a parametric search of comparable parts. Informational Advantiv Advanced TV Solutions EVALUATION KITS Solutions Bulletins & Brochures AD9751 Evaluation Board Digital to Analog Converters ICs Solutions Bulletin DOCUMENTATION DESIGN RESOURCES Application Notes AD9751 Material Declaration AN-237: Choosing DACs for Direct Digital Synthesis PCN-PDN Information AN-302: Exploit Digital Advantages in an SSB Receiver Quality And Reliability AN-320A: CMOS Multiplying DACs and Op Amps Combine Symbols and Footprints to Build Programmable Gain Amplifier, Part 1 AN-595: Understanding Pin Compatibility in the TxDAC DISCUSSIONS Line of High Speed D/A Converters View all AD9751 EngineerZone Discussions. AN-642: Coupling a Single-Ended Clock Source to the Differential Clock Input of Third-Generation TxDAC and SAMPLE AND BUY TxDAC+ Products Visit the product page to see pricing options. Data Sheet AD9751: 10-Bit, 300 MSPS High-Speed TxDAC+ D/A TECHNICAL SUPPORT Converter Data Sheet Submit a technical question or find your regional support number. TOOLS AND SIMULATIONS AD9751 IBIS Models DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.