10-Bit, 300 MSPS a High Speed TxDAC+ D/A Converter * AD9751 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-Bit Dual Muxed Port DAC DVDD DCOM AVDD ACOM 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist 25 MHz Output: 64 dB LATCH PORT1 I OUTA Internal Clock Doubling PLL MUX DAC Differential or Single-Ended Clock Input I PORT2 LATCH OUTB On-Chip 1.2 V Reference Single 3.3 V Supply Operation CLK+ REFIO Power Dissipation: 155 mW 3.3 V PLL CLK REFERENCE FSADJ CLOCK CLKVDD 48-Lead LQFP MULTIPLIER PLLVDD CLKCOM AD9751 APPLICATIONS Communications: LMDS, LMCS, MMDS RESET LPF DIV0 DIV1 PLLLOCK Base Stations Digital Synthesis QAM and OFDM PRODUCT DESCRIPTION The DAC utilizes a segmented current source architecture com- The AD9751 is a dual muxed port, ultrahigh speed, single- bined with a proprietary switching technique to reduce glitch channel, 10-bit CMOS DAC. It integrates a high quality 10-bit energy and maximize dynamic accuracy. Differential current TxDAC+ core, a voltage reference, and digital interface circuitry outputs support single-ended or differential applications. The into a small 48-lead LQFP package. The AD9751 offers excep- differential outputs each provide a nominal full-scale current tional ac and dc performance while supporting update rates up from 2 mA to 20 mA. to 300 MSPS. The AD9751 is manufactured on an advanced low cost 0.35 m The AD9751 has been optimized for ultrahigh speed applica- CMOS process. It operates from a single supply of 3.0 V to 3.6 V tions up to 300 MSPS where data rates exceed those possible on and consumes 155 mW of power. a single data interface port DAC. The digital interface consists of two buffered latches as well as control logic. These latches PRODUCT HIGHLIGHTS can be time multiplexed to the high speed DAC in several ways. 1. The AD9751 is a member of a pin compatible family of high This PLL drives the DAC latch at twice the speed of the exter- speed TxDAC+s, providing 10-, 12-, and 14-bit resolution. nally applied clock and is able to interleave the data from the 2. Ultrahigh Speed 300 MSPS Conversion Rate. two input channels. The resulting output data rate is twice that 3. Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751 of the two input channels. With the PLL disabled, an external features a flexible digital interface allowing high speed data 2 clock may be supplied and divided by two internally. conversion through either a single or dual port input. The CLK inputs (CLK+/CLK) can be driven either differen- 4. Low Power. Complete CMOS DAC function operates on tially or single-ended, with a signal swing as low as 1 V p-p. 155 mW from a 3.0 V to 3.6 V single supply. The DAC full- scale current can be reduced for lower power operation. 5. On-Chip Voltage Reference. The AD9751 includes a 1.20 V temperature compensated band gap voltage reference. *Protected by U.S. Patent numbers 5450084, 5568145, 5689257, and 5703519. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. DAC LATCHAD9751SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted.) MIN MAX OUTFS Parameter Min Typ Max Unit RESOLUTION 10 Bits 1 DC ACCURACY Integral Linearity Error (INL) 1 0.3 +1 LSB Differential Nonlinearity (DNL) 0.5 0.2 +0.5 LSB ANALOG OUTPUT Offset Error 0.025 0.01 +0.025 % of FSR Gain Error (Without Internal Reference) 5 0.5 +2 % of FSR Gain Error (With Internal Reference) 7 0.25 +2 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range 1.0 +1.25 V Output Resistance 100 k Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 M TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/C Gain Drift (Without Internal Reference) 50 ppm of FSR/C Gain Drift (With Internal Reference) 100 ppm of FSR/C Reference Voltage Drift 50 ppm/C POWER SUPPLY Supply Voltages AVDD 3.0 3.3 3.6 V DVDD 3.0 3.3 3.6 V PLLVDD 3.0 3.3 3.6 V CLKVDD 3.0 3.3 3.6 V 4 Analog Supply Current (I ) 33 36 mA AVDD 4 Digital Supply Current (I ) 3.5 4.5 mA DVDD 4 PLL Supply Current (I ) 4.5 5.1 mA PLLVDD 4 Clock Supply Current (I ) 10.0 11.5 mA CLKVDD 4 Power Dissipation (3 V, I = 20 mA) 155 165 mW OUTFS 5 Power Dissipation (3 V, I = 20 mA) 216 mW OUTFS 6 Power Supply Rejection Ratio AVDD 0.1 +0.1 % of FSR/V 6 Power Supply Rejection Ratio DVDD 0.04 +0.04 % of FSR/V OPERATING RANGE 40 +85 C NOTES 1 Measured at I , driving a virtual ground. OUTA 2 Nominal full-scale current, I , is 32 the I current. OUTFS REF 3 An external buffer amplifier is recommended to drive any external load. 4 100 MSPS f with PLL on, f = 1 MHz, all supplies = 3.0 V. DAC OUT 5 300 MSPS f . DAC 6 5% power supply variation. Specifications subject to change without notice. 2 REV. C