12-Bit, 125 MSPS High Performance a TxDAC D/A Converter AD9752* FEATURES FUNCTIONAL BLOCK DIAGRAM +5V High Performance Member of Pin-Compatible TxDAC Product Family REFLO AVDD ACOM 150pF 125 MSPS Update Rate +1.20V REF AD9752 0.1mF 12-Bit Resolution REFIO 0.1mF CURRENT ICOMP Excellent Spurious Free Dynamic Range Performance FS ADJ SOURCE ARRAY SFDR to Nyquist 5 MHz Output: 79 dBc R SET +5V DVDD IOUTA Differential Current Outputs: 2 mA to 20 mA LSB SEGMENTED DCOM IOUTB SWITCHES SWITCHES Power Dissipation: 185 mW 5 V CLOCK Power-Down Mode: 20 mW 5 V CLOCK LATCHES SLEEP On-Chip 1.20 V Reference DIGITAL DATA INPUTS (DB11DB0) CMOS-Compatible +2.7 V to +5.5 V Digital Interface Package: 28-Lead SOIC and TSSOP The AD9752 is a current-output DAC with a nominal full-scale Edge-Triggered Latches output current of 20 mA and > 100 kW output impedance. APPLICATIONS Differential current outputs are provided to support single- Wideband Communication Transmit Channel: ended or differential applications. Matching between the two Direct IF current outputs ensures enhanced dynamic performance in a Basestations differential output configuration. The current outputs may be Wireless Local Loop tied directly to an output resistor to provide two complemen- Digital Radio Link tary, single-ended voltage outputs or fed directly into a trans- Direct Digital Synthesis (DDS) former. The output voltage compliance range is 1.25 V. Instrumentation The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9752 can be driven PRODUCT DESCRIPTION by the on-chip reference or by a variety of external reference The AD9752 is a 12-bit resolution, wideband, second generation voltages. The internal control amplifier, which provides a wide member of the TxDAC series of high performance, low power (>10:1) adjustment span, allows the AD9752 full-scale current CMOS digital-to-analog-converters (DACs). The TxDAC family, to be adjusted over a 2 mA to 20 mA range while maintaining which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is excellent dynamic performance. Thus, the AD9752 may oper- specifically optimized for the transmit signal path of communica- ate at reduced power levels or be adjusted over a 20 dB range to tion systems. All of the devices share the same interface options, provide additional gain ranging capabilities. small outline package and pinout, thus providing an upward or downward component selection path based on performance, The AD9752 is available in 28-lead SOIC and TSSOP packages. resolution and cost. The AD9752 offers exceptional ac and dc It is specified for operation over the industrial temperature range. performance while supporting update rates up to 125 MSPS. PRODUCT HIGHLIGHTS The AD9752s flexible single-supply operating range of 4.5 V to 1. The AD9752 is a member of the wideband TxDAC product 5.5 V and low power dissipation are well suited for portable and family that provides an upward or downward component selec- low power applications. Its power dissipation can be further tion path based on resolution (8 to 14 bits), performance and reduced to a mere 65 mW, without a significant degradation in cost. The entire family of TxDACs is available in industry performance, by lowering the full-scale current output. Also, a standard pinouts. power-down mode reduces the standby power dissipation to 2. Manufactured on a CMOS process, the AD9752 uses a approximately 20 mW. proprietary switching technique that enhances dynamic The AD9752 is manufactured on an advanced CMOS process. performance beyond that previously attainable by higher A segmented current source architecture is combined with a power/cost bipolar or BiCMOS devices. proprietary switching technique to reduce spurious components 3. On-chip, edge-triggered input CMOS latches interface readily and enhance dynamic performance. Edge-triggered input latches to +2.7 V to +5 V CMOS logic families. The AD9752 can and a 1.2 V temperature compensated bandgap reference have support update rates up to 125 MSPS. been integrated to provide a complete monolithic DAC solution. 4. A flexible single-supply operating range of 4.5 V to 5.5 V and The digital inputs support +2.7 V to +5 V CMOS logic families. a wide full-scale current adjustment span of 2 mA to 20 mA TxDAC is a registered trademark of Analog Devices, Inc. *Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and allow the AD9752 to operate at reduced power levels. 5703519. 5. The current output(s) of the AD9752 can be easily config- REV. 0 ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD9752SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 12 Bits 1 DC ACCURACY Integral Linearity Error (INL) T = +25 C 1.5 0.5 +1.5 LSB A T to T 2.0 +2.0 LSB MIN MAX Differential Nonlinearity (DNL) T = +25 C 0.75 0.25 +0.75 LSB A T to T 1.0 +1.0 LSB MIN MAX ANALOG OUTPUT Offset Error 0.02 +0.02 % of FSR Gain Error (Without Internal Reference) 2 0.5 +2 % of FSR Gain Error (With Internal Reference) 5 1.5 +5 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range 1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/ C Gain Drift (Without Internal Reference) 50 ppm of FSR/ C Gain Drift (With Internal Reference) 100 ppm of FSR/ C Reference Voltage Drift 50 ppm/ C POWER SUPPLY Supply Voltages AVDD 4.5 5.0 5.5 V DVDD 2.7 5.0 5.5 V 4 Analog Supply Current (I ) 34 39 mA AVDD 5 Digital Supply Current (I ) 35 mA DVDD 6 Supply Current Sleep Mode (I ) 48 mA AVDD 5 Power Dissipation (5 V, I = 20 mA) 185 220 mW OUTFS 7 Power Supply Rejection Ratio AVDD 0.4 +0.4 % of FSR/V 7 Power Supply Rejection Ratio DVDD 0.025 +0.025 % of FSR/V OPERATING RANGE 40 +85 C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Requires +5 V supply. 5 Measured at f = 25 MSPS and I = static full scale (20 mA). CLOCK OUT 6 Logic level for SLEEP pin must be referenced to AVDD. Min V = 3.5 V. IH 7 5% Power supply variation. Specifications subject to change without notice. REV. 0 2