10-Bit, 125 MSPS a TxDAC D/A Converter AD9760 FUNCTIONAL BLOCK DIAGRAM FEATURES Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1 F 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance REFLO COMP1 AVDD ACOM SFDR to Nyquist 40 MHz Output: 52 dBc +1.20V REF AD9760 50pF 0.1 F Differential Current Outputs: 2 mA to 20 mA REFIO 0.1 F CURRENT COMP2 Power Dissipation: 175 mW 5 V to 45 mW 3 V SOURCE FS ADJ ARRAY Power-Down Mode: 25 mW 5 V R SET On-Chip 1.20 V Reference +5V DVDD I OUTA SEGMENTED LSB Single +5 V or +3 V Supply Operation DCOM I OUTB SWITCHES SWITCHES Packages: 28-Lead SOIC and TSSOP CLOCK Edge-Triggered Latches CLOCK LATCHES SLEEP APPLICATIONS DIGITAL DATA INPUTS (DB9DB0) Communication Transmit Channel: Basestations The AD9760 is a current-output DAC with a nominal full-scale Set Top Boxes output current of 20 mA and > 100 k output impedance. Digital Radio Link Differential current outputs are provided to support single- Direct Digital Synthesis (DDS) ended or differential applications. Matching between the two Instrumentation current outputs ensures enhanced dynamic performance in a PRODUCT DESCRIPTION differential output configuration. The current outputs may be The AD9760 and AD9760-50 are the 10-bit resolution members tied directly to an output resistor to provide two complemen- of the TxDAC series of high performance, low power CMOS tary, single-ended voltage outputs or fed directly into a trans- digital-to-analog converters (DACs). The AD9760-50 is a lower former. The output voltage compliance range is 1.25 V. performance option that is guaranteed and specified for 50 MSPS The on-chip reference and control amplifier are configured for operation. The TxDAC family that consists of pin compatible 8-, maximum accuracy and flexibility. The AD9760 can be driven 10-, 12- and 14-bit DACs is specifically optimized for the trans- by the on-chip reference or by a variety of external reference mit signal path of communication systems. All of the devices voltages. The internal control amplifier that provides a wide share the same interface options, small outline package and (>10:1) adjustment span allows the AD9760 full-scale current pinout, thus providing an upward or downward component to be adjusted over a 2 mA to 20 mA range while maintaining selection path based on performance, resolution and cost. Both excellent dynamic performance. Thus, the AD9760 may oper- the AD9760 and AD9760-50 offer exceptional ac and dc ate at reduced power levels or be adjusted over a 20 dB range to performance while supporting update rates up to 125 MSPS provide additional gain ranging capabilities. and 60 MSPS respectively. The AD9760 is available in a 28-lead SOIC and TSSOP packages. The AD9760s flexible single-supply operating range of 2.7 V to It is specified for operation over the industrial temperature range. 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further PRODUCT HIGHLIGHTS reduced to a mere 45 mW without a significant degradation in 1. The AD9760 is a member of the TxDAC product family that performance by lowering the full-scale current output. Also, a provides an upward or downward component selection path power-down mode reduces the standby power dissipation to based on resolution (8 to 14 bits), performance and cost. approximately 25 mW. 2. Manufactured on a CMOS process, the AD9760 uses a pro- The AD9760 is manufactured on an advanced CMOS process. A prietary switching technique that enhances dynamic perfor- segmented current source architecture is combined with a propri- mance beyond what was previously attainable by higher etary switching technique to reduce spurious components and power/cost bipolar or BiCMOS devices. enhance dynamic performance. Edge-triggered input latches and a 3. On-chip, edge-triggered input CMOS latches interface readily 1.2 V temperature compensated bandgap reference have been inte- to +3 V and +5 V CMOS logic families. The AD9760 can grated to provide a complete monolithic DAC solution. Flexible support update rates up to 125 MSPS. supply options support +3 V and +5 V CMOS logic families. 4. A flexible single-supply operating range of 2.7 V to 5.5 V and TxDAC is a registered trademark of Analog Devices, Inc. a wide full-scale current adjustment span of 2 mA to 20 mA allow the AD9760 to operate at reduced power levels. REV. B 5. The current output(s) of the AD9760 can be easily config- Information furnished by Analog Devices is believed to be accurate and ured for various single-ended or differential circuit topologies. reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD9760/AD9760-50SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) DC SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 10 Bits 1 DC ACCURACY Integral Linearity Error (INL) 1.0 0.5 +1.0 LSB Differential Nonlinearity (DNL) 0.5 0.25 +0.5 LSB MONOTONICITY Guaranteed Over Specified Temperature Range ANALOG OUTPUT Offset Error 0.025 +0.025 % of FSR Gain Error (Without Internal Reference) 10 2 +10 % of FSR Gain Error (With Internal Reference) 10 1 +10 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range 1.0 1.25 V Output Resistance 100 k Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 M 4 Small Signal Bandwidth (w/o C ) 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/C Gain Drift (Without Internal Reference) 50 ppm of FSR/C Gain Drift (With Internal Reference) 100 ppm of FSR/C Reference Voltage Drift 50 ppm/C POWER SUPPLY Supply Voltages 5 AVDD 2.7 5.0 5.5 V DVDD 2.7 5.0 5.5 V Analog Supply Current (I)2530mA AVDD 6 Digital Supply Current (I ) 35 mA DVDD Supply Current Sleep Mode (I ) 8.5 mA AVDD 6 Power Dissipation (5 V, I = 20 mA) 140 175 mW OUTFS 7 Power Dissipation (5 V, I = 20 mA) 190 mW OUTFS 7 Power Dissipation (3 V, I = 2 mA) 45 mW OUTFS Power Supply Rejection RatioAVDD 0.04 +0.04 % of FSR/V Power Supply Rejection RatioDVDD 0.025 +0.025 % of FSR/V OPERATING RANGE 40 +85 C NOTES 1 Measured at I , driving a virtual ground. OUTA 2 Nominal full-scale current, I , is 32 the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at f = 50 MSPS and f = 1.0 MHz. CLOCK OUT 7 Measured as unbuffered voltage output into 50 R at I and I , f = 100 MSPS and f = 40 MHz. LOAD OUTA OUTB CLOCK OUT Specifications subject to change without notice. 2 REV. B